ISR Data Transport Packets for CRC-Based Time Synchronization
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Solution Overview
Problem
ISR systems face limitations in data integrity and time synchronization across multiple domains due to physical network interface restrictions and non-standard processor configurations, which hinder system performance and timing synchronization.
Innovation Solution
A multi-processor computer system and method for ensuring data integrity and time synchronization across a multi-domain operational platform, utilizing a control node and remote node with packet-based data transfer protocols, CRC verification, and time synchronization mechanisms to maintain accurate timing across high-speed serial links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical network interfaces are used to connect processors in ISR systems, then data transmission can be established, but the available locations of processors are restricted and timing synchronization performance deteriorates
Solution Approach 1:
The patent replaces physical network interface connections with a wireless communication system. Processors communicate via wireless signals rather than physical cables, eliminating the mechanical constraint of fixed processor locations while maintaining data transmission capability. This allows processors to be positioned flexibly within the service area of the synchronization signal.
Solution Approach 2:
The synchronization signal serves multiple functions simultaneously: it provides timing synchronization, establishes data transmission channels, and enables processor location flexibility. This multi-functional approach resolves the contradiction by making the system adaptable to various processor configurations while maintaining reliable data integrity through the universal synchronization mechanism.
2Reliability
If physical network interfaces are used to connect processors in ISR systems, then data transmission can be established, but timing synchronization performance deteriorates
Solution Approach 1:
The patent replaces physical network interface timing with wireless synchronization signal timing. The synchronization signal is distributed wirelessly with precise timing information, allowing processors to achieve accurate timing synchronization without being constrained by physical network interface limitations and cable delays.
Solution Approach 2:
The master processor generates synchronization signals that are copied and distributed to slave processors. Each slave processor receives an identical copy of the synchronization signal, ensuring timing accuracy is maintained across all processors without degradation from physical interface variations.
3Adaptability or versatility
If non-standard processor configurations are used, then system adaptability increases, but the ability to use common architectural elements and algorithms decreases
Solution Approach 1:
The synchronization signal provides a universal interface that works with non-standard processor configurations. By establishing a common timing reference through wireless signals, the system enables processors with different architectures to communicate effectively, reducing complexity associated with custom integration while maintaining adaptability.
Data Source
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AI summary
A computer system is provided that includes devices configured to acquire input data. The system further includes a remote node (RN) (104) configured to receive a first packet from a control node (CN) (102). The first packet includes a packet header including a master timestamp, first control data and a CRC. The RN is also configured to verify integrity of the first control data based on the received CRC, generate and transmit to the CN a second packet. The second packet includes a packet header which includes a remote timestamp. The system also includes a CN connected with the RN (104) via high-speed serial interfaces. The CN (102) is configured to receive the second packet, determine status of the first packet based on the control data included in the second packet and configured to retransmit the first packet or generate and transmit a third packet based on the determined status of the first packet.