ISR Prefetch Control Circuit for Multicore Processor Latency
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Solution Overview
Problem
In conventional multicore processor-based systems, interrupt handling is hindered by delays such as processor cores being in low-power mode, context-saving operations, and the need to fetch ISRs from system memory, leading to increased latency and disruption of tasks.
Innovation Solution
Implementing an ISR prefetch control circuit that communicatively couples with an interrupt controller and instruction fetch units to prefetch ISRs on a less busy processor core, storing them in a shared cache for later retrieval, thereby reducing latency and improving system performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If ISRs are permanently placed in cache memory to avoid fetching from system memory, then interrupt latency is reduced, but cache memory available for other instructions is reduced or cache memory area and power consumption increases
Solution Approach 1:
The patent applies preliminary action by prefetching ISR instructions into the instruction cache before they are actually needed for execution. When an interrupt is detected, the system proactively fetches the corresponding ISR from system memory into the instruction cache in advance, so that when the interrupt service routine needs to be executed, the instructions are already available in the cache, thereby reducing interrupt latency without permanently dedicating cache space to ISRs
Solution Approach 2:
The patent implements dynamics by making the cache memory usage dynamic rather than static. Instead of permanently allocating cache space for ISRs, the system dynamically loads ISR instructions into the cache only when needed (upon interrupt detection) and allows the cache to be used for other instructions during normal operation. This dynamic approach optimizes the trade-off between interrupt latency and cache availability
2Use of energy by moving object
If a processor core in low-power mode receives an interrupt, then power consumption is reduced during idle periods, but interrupt handling is delayed while the processor core is woken up
Solution Approach 1:
The patent applies preliminary action by preparing the ISR instructions in advance and storing them in the instruction cache before the processor core needs to execute them. This way, when an interrupt occurs during low-power mode, the wake-up process can proceed faster because the ISR instructions are already available in the cache, reducing the time penalty associated with exiting low-power mode
3Measurement precision
If the top-level exception handler includes context-saving operations to identify the specific ISR, then interrupt accuracy is improved, but considerable delay is incurred
Solution Approach 1:
The patent applies preliminary action by pre-fetching and caching the ISR instructions before the context-saving operations are completed. The system uses the interrupt request identifier to proactively load the corresponding ISR into the instruction cache during the interrupt acknowledgment phase, so that when the top-level exception handler completes its context-saving operations and needs to execute the specific ISR, the instructions are already ready in the cache, thereby reducing the time delay without compromising interrupt identification accuracy
Data Source
AI summary
Providing interrupt service routine (ISR) prefetching in multicore processor-based systems is disclosed. In one aspect, a multicore processor-based system provides an ISR prefetch control circuit communicatively coupled to an interrupt controller and a plurality of instruction fetch units (IFUs) of a corresponding plurality of processor elements (PEs). Upon receiving an interrupt directed to a target PE of the plurality of PEs, the interrupt controller provides an interrupt request (IRQ) identifier to the ISR prefetch control circuit. Based on the IRQ identifier, the ISR prefetch control circuit fetches an ISR pointer to an ISR corresponding to the IRQ identifier. The ISR prefetch control circuit next selects a prefetch PE of the plurality of PEs to perform a prefetch operation to retrieve the ISR on behalf of the target PE, and provides an ISR prefetch request, including the ISR pointer, to an IFU of the prefetch PE.