Microprocessor Issue Queue Back-to-Back Instruction Wake-Up
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Solution Overview
Problem
Conventional superscalar processors face timing critical paths due to instruction tag comparisons after a producer instruction has been selected for issue, which hinders optimal issue bandwidth when issuing instructions with operand dependencies.
Innovation Solution
The processor employs an issue queue with a target table and 'consumer_qpos' bit field to track operand dependencies by associating pointers between instructions, allowing dependent instructions to be woken up immediately after the producer instruction's issue, eliminating the need for extra clock cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor compares instruction tags after the producer instruction has been selected for issue to identify dependent instructions, then data dependencies are correctly tracked, but a timing critical path is created that prevents optimal issue bandwidth
Solution Approach 1:
The patent performs dependency tracking by comparing instruction tags during the instruction dispatch phase, before the producer instruction is selected for issue. This preliminary action populates a target table with target instruction tags and associates consumer queue positions with producer instructions. When the producer instruction is later issued, the dependent instructions are already identified and can be immediately woken up, eliminating the timing critical path that would otherwise exist if tag comparisons were performed after issue selection.
2Productivity
If the processor issues dependent instructions in the cycle immediately following the producer instruction, then optimal issue bandwidth is achieved, but this creates a timing critical path due to post-issue tag comparisons
Solution Approach 1:
The patent performs dependency tracking by comparing instruction tags during the instruction dispatch phase, before the producer instruction is selected for issue. This preliminary action populates a target table with target instruction tags and associates consumer queue positions with producer instructions. When the producer instruction is later issued, the dependent instructions are already identified and can be immediately woken up, eliminating the timing critical path that would otherwise exist if tag comparisons were performed after issue selection.
Solution Approach 2:
The patent introduces a target table as an intermediary data structure that stores target instruction tags and consumer queue positions. This table acts as a mediator between the instruction dispatch unit and the issue queue, allowing dependency information to be pre-computed and stored. When a producer instruction is issued, the target table enables rapid retrieval of dependent instruction positions without requiring real-time tag comparisons, thus eliminating the timing critical path while maintaining optimal issue bandwidth.
Data Source
AI summary
Techniques are disclosed for back-to-back issue of instructions in a processor. A first instruction is stored in a queue position in an issue queue. The issue queue stores instructions in a corresponding queue position. The first instruction includes a target instruction tag and at least a source instruction tag. The target instruction tag is stored in a table storing a plurality of target instruction tags associated with a corresponding instruction. Each stored target instruction tag specifies a logical register that stores a target operand. Upon determining, based on the source instruction tag associated with the first instruction and the target instruction tag associated with a second instruction, that the first instruction is dependent on the second instruction, a pointer to the first instruction is associated with the second instruction. The pointer is used to wake up the first instruction upon issue of the second instruction.