In-System Test Mechanism for Chip Structural Fault Detection
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Solution Overview
Problem
Current methods for testing chips in the field are inadequate for detecting structural faults that can occur during the lifetime of safety-critical products like autonomous vehicles, as they lack granularity in diagnosis and are limited in flexibility and scalability.
Innovation Solution
An in-system test (IST) mechanism that uses a combination of hardware and software components to enable self-testing of integrated circuits, allowing for flexible updates of test patterns and conditions, and supports various fault models, enabling detection of structural faults in real-world environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If functional patterns are used for testing chips in the field, then testing can be performed after shipping, but the testing methods have long development cycles and are difficult to quantify for fault coverage
Solution Approach 1:
The patent applies preliminary action by pre-configuring multiple test patterns and fault models in the test device before field deployment. The system stores various test patterns (including stuck-at, transition, and delay fault models) and pre-compiles test sequences, allowing immediate execution without lengthy development cycles when chips are tested in the field.
Solution Approach 2:
The patent implements dynamics by enabling the test device to dynamically select and switch between different test patterns and fault models based on the specific chip being tested and the type of defects suspected. The system can adaptively choose from multiple pre-loaded test sequences, making the testing process flexible and efficient rather than static and time-consuming.
2Reliability
If functional patterns are used for testing, then testing can be performed in the field, but the methods lack granularity in the diagnosis of failures
Solution Approach 1:
The patent applies segmentation by dividing the testing process into multiple granular levels: different fault models (stuck-at, transition, delay), multiple test patterns for each model, and hierarchical test sequences that can isolate specific circuit regions. This segmented approach enables precise localization of failures to specific circuit elements rather than providing only coarse functional failure information.
Solution Approach 2:
The patent implements local quality by providing different test patterns targeted at specific circuit characteristics and potential failure modes. Each test pattern is designed with specific properties to detect particular types of defects in specific circuit regions, allowing the system to apply the most appropriate diagnostic method locally to each suspected failure area.
3Extent of automation
If logic and memory built-in self-test (BIST) methods are used, then testing can be performed autonomously, but the techniques support only a fixed set of tests and fault models which cannot be modified in the field
Solution Approach 1:
The patent applies universality by designing a test device that can perform multiple testing functions through a single unified architecture. The system supports various fault models (stuck-at, transition, delay), multiple test patterns, and different circuit types (logic, memory, mixed-signal) within one device, allowing autonomous operation while maintaining high adaptability to different testing requirements.
Solution Approach 2:
The patent implements dynamics by enabling the autonomous test device to dynamically configure its testing behavior based on the specific chip under test. The system can selectively activate different fault models and test patterns from its pre-loaded library, and can adaptively adjust test parameters and sequences based on real-time test results and identified failure modes.
Data Source
AI summary
Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.