Two-Qubit iSWAP Cascade Schedule for Leakage-Suppressed Gates
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Solution Overview
Problem
Existing methods for implementing iSWAP gates in quantum computers are slow and prone to leakage errors, making them inefficient and difficult to execute in near-term quantum computing architectures.
Innovation Solution
A cascade schedule is implemented that adiabatically drives detuning between qubit frequencies through avoided crossings in both leakage and swap channels, using a trapezoidal ramp function and polynomial expansion of the control angle to minimize errors and achieve high fidelity SWAP operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing methods are used to execute iSWAP gates, then the gate can be implemented, but the execution is slow and prone to leakage errors
Solution Approach 1:
The gate execution is divided into multiple discrete stages (first stage, second stage, third stage, fourth stage, fifth stage), each targeting specific error channels. The cascade schedule segments the detuning trajectory to separately address leakage channel avoided crossings and swap channel avoided crossings, allowing optimized control for each segment.
Solution Approach 2:
The patent employs dynamic parameter changes including detuning frequency modulation, control angle variation through polynomial expansion, and timing parameter optimization. The cascade schedule modifies detuning parameters through multiple avoided crossings while polynomial expansion adjusts control angle parameters to synchronize error suppression.
2Reliability
If adiabatic evolution is used to suppress leakage errors, then reliability improves, but the gate duration increases
Solution Approach 1:
The adiabatic evolution process is segmented into distinct stages with different priorities. The first stage and fifth stage handle leakage channel avoided crossings adiabatically, while the second stage and fourth stage handle swap channel avoided crossings. The third stage provides a plateau for evolution, creating a segmented temporal structure that balances adiabatic requirements with gate speed.
Solution Approach 2:
The cascade schedule implements periodic action through reverse ordering of stages. The fourth stage implements the second stage in reverse order, and the fifth stage implements the first stage in reverse order, creating a symmetric periodic structure that reinforces error suppression while controlling overall duration.
3Device complexity
If simple gate schedules are used, then device complexity is reduced, but error synchronization and fidelity are compromised
Solution Approach 1:
Polynomial expansion serves as an intermediary mathematical tool that translates simple control angle specifications into complex time-dependent control waveforms. The cascade schedule acts as an intermediary control strategy that coordinates multiple detuning parameters to simultaneously address leakage and swap channel errors without requiring direct complex hardware control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in fast and robust iSWAP gate execution with leakage error suppression below 10^-4, achieving fidelity exceeding 99.9999% and reducing circuit design complexity, facilitating scalable quantum computing.
Implementation Method 1
during a first stage, adiabatically driving detuning between the frequency of the first qubit and the frequency of the second qubit through a first avoided crossing in a leakage channel
Implementation Method 2
during a second stage, driving detuning between the frequency of the first qubit and the frequency of the second qubit through a second avoided crossing in a swap channel
Data Source
AI summary
Methods, systems and apparatus for implementing iSWAP quantum logic gates between a first qubit and a second qubit. In one aspect, a method includes implementing a cascade schedule that defines a trajectory of a detuning between a frequency of the first qubit and a frequency of the second qubit. Implementing the cascade schedule includes: during a first stage, adiabatically driving detuning between the frequency of the first qubit and the frequency of the second qubit through a first avoided crossing in a leakage channel; during a second stage, driving detuning between the frequency of the first qubit and the frequency of the second qubit through a second avoided crossing in a swap channel; during a third stage, evolving the first qubit and second qubit; during a fourth stage, implementing the second stage in reverse order; and during a fifth stage, implementing the first stage in reverse order.