Iterative Decoder Memory Gating for Lower Read-Write Frequency
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Solution Overview
Problem
Traditional decoder circuits and flash memory controllers face challenges in meeting system-level memory bandwidth requirements due to process yield limitations, leading to high power consumption during iterative decoding in high-noise environments, especially when reading and writing all small physical memories simultaneously.
Innovation Solution
A decoder circuit and flash memory controller design that includes variable and check node circuits, syndrome calculation, and memory macros, which dynamically control memory operations by dividing data into blocks and skipping unnecessary read/write operations based on data changes, reducing the frequency of memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If all small physical memories are read and written simultaneously during iterative decoding, then the memory bandwidth requirement is met, but power consumption increases significantly
Solution Approach 1:
The patent divides the memory system into multiple small physical memories (first physical sub-memories and second physical sub-memories) and processes data in blocks. By segmenting the memory access operations and processing different blocks in an iterative decoding manner, the system can meet bandwidth requirements through parallel processing while reducing power consumption by not accessing all memories simultaneously in high-noise environments.
Solution Approach 2:
The patent implements dynamic control of memory read/write operations based on decoding requirements. The system dynamically activates or skips memory access operations during iterative decoding, adjusting the number of active memory operations based on the current decoding state and noise conditions, thereby reducing power consumption while maintaining necessary bandwidth.
2Reliability
If iterative decoding is performed in high-noise environment, then error correction capability is improved, but power consumption increases due to frequent memory operations
Solution Approach 1:
The patent employs periodic iterative decoding operations where memory read/write actions are performed in cycles rather than continuously. The system performs a series of iterative decoding steps with periodic memory access patterns, allowing error correction to accumulate over multiple passes while reducing the instantaneous power demand compared to continuous full-memory access.
Solution Approach 2:
The system dynamically adjusts the intensity and frequency of memory operations during iterative decoding based on the decoded data quality and noise levels. When error correction progresses successfully, the system can reduce memory access frequency, thereby lowering power consumption while maintaining reliability.
3Use of energy by moving object
If data is divided into blocks and selective memory operations are performed, then power consumption is reduced, but system complexity increases
Solution Approach 1:
The patent divides data into blocks and memories into sub-memories, creating a structured segmentation that simplifies control logic. Each block can be processed independently with standardized control signals, reducing the overall control complexity despite the increased operational selectivity. The segmented architecture allows for modular control units that manage individual blocks without requiring complex global coordination.
Data Source
AI summary
A decoding method includes: generating a variable-to-check message and a log-likely ratio according a specific codeword; converting the variable-to-check message from variable node domain into check node domain to generate a converted variable-to-check message; generating a check-to-variable message according to the converted variable-to-check message; converting the check-to-variable message from check node domain into variable node domain to generate a converted check-to-variable message; updating the variable-to-check message and the log-likely ratio based on the converted check-to-variable message; performing a hard decision according to the log-likely ratio to determine whether flip bit(s); and, for specific data to be stored into a first memory macro, enabling a write operation of a portion of first physical sub-memories and disabling a write operation of another portion of first physical sub-memories.