Iterative Decoder Node Control for Lower Peak Power
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Solution Overview
Problem
Iterative decoding in forward error correction (FEC) circuits, such as LDPC decoding, leads to high power consumption, which is a significant drawback as it can account for 50% or more of a chip's power consumption due to increased complexity and decoding frequency.
Innovation Solution
A method to control power consumption in iterative decoders by progressively enabling and disabling check node and variable node processors, along with their corresponding memories, using a controller to manage the number of processing units during decoding operations, thereby reducing supply voltage variation and optimizing power usage based on criteria like signal-to-noise ratio and decoding convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If iterative decoding is performed with high decoding frequency and many iterations to achieve high performance and high bit decoding throughput, then decoding performance is improved, but power consumption increases significantly (50% or more of entire chip's power consumption)
Solution Approach 1:
The patent applies dynamics by making the number of active check node processors variable rather than fixed. The controller dynamically adjusts the number of active check node processors based on decoding progress and performance requirements, enabling the system to adapt power consumption to actual needs while maintaining high throughput when necessary.
Solution Approach 2:
The patent changes the parameter of the number of active check node processors from a constant value to a variable parameter that can be adjusted during operation. By modifying this parameter based on decoding convergence and performance metrics, the system optimizes the trade-off between throughput and power consumption.
2Use of energy by moving object
If the number of check node processors is reduced to lower power consumption, then power consumption is decreased, but decoding performance and throughput may be compromised
Solution Approach 1:
The system dynamically adjusts the number of active check node processors based on real-time decoding performance and convergence metrics. When decoding is progressing well, fewer processors are activated to reduce power consumption. When performance degradation is detected, the system can activate more processors to maintain throughput, thus dynamically balancing power and performance.
Solution Approach 2:
The controller preliminarily determines the optimal number of active check node processors based on expected decoding requirements and channel conditions before full decoding operations begin. This preliminary configuration allows the system to start with an optimized processor count, avoiding unnecessary power consumption from excessive processors while ensuring sufficient processing capacity.
3Use of energy by moving object
If progressive enabling and disabling of check node processors is implemented to reduce power consumption, then power consumption is optimized, but control complexity increases
Solution Approach 1:
The controller implements feedback mechanisms by monitoring decoding performance metrics and convergence status, then using this information to adjust the number of active check node processors. This closed-loop control automates the complex decision-making process, reducing the perceived control complexity while achieving optimal power consumption through performance-based processor activation.
Data Source
AI summary
A method for controlling power consumption of an iterative decoder based on one or more criteria is described. The method may include progressively enabling and disabling nodes of the iterative decoder to perform iterative decoding on a demodulated signal to provide a decoded signal with minimal variation of a supply voltage.