Iterative Decoder Memory Layout for Interleaved R/Q Bank Access
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Solution Overview
Problem
Conventional memory arrangements for iterative decoders, such as those used in Low Density Parity Check (LDPC) decoders, face challenges in memory density and port constraints, leading to larger memory areas and inefficiencies in data processing.
Innovation Solution
The proposed solution involves a memory module with a single R memory component and two Q memory banks, along with a channel detector memory component, which allows for efficient storage and communication of data associated with current and previous codewords, utilizing a Soft Output Viterbi Algorithm (SOVA) and extrinsic channel log-likelihood-ratio memory to improve memory density and reduce port requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory arrangements with multiple separate memory banks are used, then data storage capacity is sufficient, but memory area increases and device complexity increases
Solution Approach 1:
The patent combines multiple separate memory banks (R memory and Q memory) into a single unified memory structure. The memory module uses a single memory array that stores both R data (check node to bit node messages) and Q data (bit node to check node messages) for current and previous codewords, eliminating the need for separate memory banks and reducing overall memory area while maintaining full storage capacity
Solution Approach 2:
The unified memory structure serves multiple functions simultaneously: it stores R data and Q data for both current and previous codewords, and provides read/write access to multiple decoder components. This multi-functional memory design replaces what would traditionally require multiple specialized memory banks, reducing device complexity and memory area
2Speed
If multiple separate memory banks are used, then data access for different codewords is efficient, but the number of ports increases and device complexity increases
Solution Approach 1:
The patent introduces a time dimension to memory addressing by storing data for current and previous codewords in the same memory array using different address spaces. This allows the single memory module to provide efficient data access for multiple codewords simultaneously by leveraging temporal separation rather than requiring separate spatial memory banks, thus maintaining access efficiency while reducing port requirements
Solution Approach 2:
The memory module dynamically switches between storing and accessing data for current and previous codewords based on decoding stage requirements. The unified memory structure can be configured through addressing schemes to provide efficient access to whichever codeword data is currently needed, replacing static multiple memory bank architectures with a dynamic single memory system
Data Source
AI summary
The present disclosure includes apparatus, systems and techniques relating to iterative decoder memory arrangement. A described apparatus includes R banks; Q banks; circuitry configured to store R data for a current codeword in a first R bank of the R banks and store R data for a previous codeword in a second R bank of the R banks; circuitry configured to alternate among the R banks for storing current codeword R data; circuitry configured to store Q data for the current codeword in a first Q bank of the Q banks and store Q data for the previous codeword in a second Q bank of the Q banks; and circuitry configured to alternate among the Q banks for storing current codeword Q data. The apparatus can include circuitry configured to interleave read accesses among the R banks.