Iterative Decoder Pipelining and Voltage Scaling for Lower Power
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Solution Overview
Problem
Iterative error correcting decoders in data communications often perform a fixed number of iterations to correct worst-case codewords, leading to excess decoding time for codewords that require fewer iterations, resulting in inefficient use of resources.
Innovation Solution
Implementing an input buffer and low-complexity combinational logic to process codewords for the minimal time required to become error-free, allowing for reallocation of decoding time and reducing the internal frequency of the decoder, thereby saving power and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed number of iterations is performed to correct worst-case codewords, then all codewords can be corrected reliably, but codewords requiring fewer iterations still consume full decoding time, reducing overall efficiency
Solution Approach 1:
The decoder dynamically adjusts the number of iterations based on the decoding progress and error correction needs of each codeword. Instead of performing a fixed number of iterations for all codewords, the system monitors decoding convergence and terminates early when errors are corrected, allocating more time to difficult codewords and less to easy ones, thereby resolving the contradiction between reliability and time efficiency
Solution Approach 2:
The system implements feedback mechanisms to monitor the decoding status of each codeword in real-time. Based on this feedback, the decoder adjusts the iteration count dynamically - stopping early when convergence is achieved and continuing longer when needed. This feedback-driven approach ensures all codewords are corrected reliably while minimizing excess decoding time for easily correctable codewords
2Productivity
If clock frequency and supply voltage are increased to reduce decoding time, then more iterations can be performed, but power consumption increases significantly
Solution Approach 1:
The system changes operational parameters dynamically - specifically adjusting clock frequency and supply voltage based on the actual decoding requirements of each codeword. Instead of maintaining high frequency and voltage for all operations, the system uses lower parameters when fewer iterations are needed and increases them only when more iterations are required, thereby maintaining productivity while significantly reducing average power consumption
Solution Approach 2:
The decoder operates dynamically by adjusting its clock frequency and supply voltage in response to decoding progress. This dynamic operation allows the system to perform more iterations when necessary without continuously consuming high power, resolving the contradiction between productivity and energy usage by matching resource allocation to actual computational needs
3Measurement precision
If more iterations are performed to improve BER performance, then decoding accuracy increases, but the complexity and power consumption of the decoder increase
Solution Approach 1:
The system applies partial action by performing only the necessary number of iterations required to achieve the target BER performance for each codeword, rather than always performing the maximum number of iterations. This approach maintains measurement precision (BER performance) while avoiding the unnecessary complexity and power consumption associated with always operating at maximum iteration capacity
Solution Approach 2:
The decoder adjusts operational parameters such as iteration count, clock frequency, and supply voltage based on the actual BER performance requirements. By changing these parameters dynamically rather than maintaining fixed high values, the system achieves the required measurement precision without incurring the full complexity and power costs of always operating at maximum performance levels
Data Source
AI summary
A decoder architecture and method for processing codewords are provided. In one implementation, the decoder architecture includes an input buffer configured to receive and store one or more codewords to be processed, and a decoder configured to receive codewords one at a time from the input buffer. The decoder processes each codeword only for a minimum amount of time for the codeword to become error free. The decoder architecture further includes an input buffer monitor and supply regulator configured to change a voltage supply to the decoder responsive to an average amount of time or each codeword to become error free.