Iterative Signal Decoding with Re-Encoding for Burst Error Correction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing signal processing methods for error correction in communication systems are complex and require hardware/software changes, with limited effectiveness in addressing noise and error conditions, particularly in burst errors.

Innovation Solution

An iterative decoding method using logic circuitry to assess error characteristics of encoded signals, assigning reliability metrics to bits, and utilizing these metrics for subsequent decoding to correct errors, employing concatenated decoding and techniques like cyclic redundancy check (CRC) and Reed-Solomon decoding.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If iterative decoding with re-encoding is implemented, then error correction capability is improved, but device complexity increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoiddecoding system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements nested decoding stages where an outer decoder (Reed-Solomon) and inner decoder (Viterbi) are arranged in a hierarchical structure with iterative feedback. The outer decoder processes blocks of bits and provides reliability information to the inner decoder, which performs convolutional decoding. This nested arrangement allows complex error correction to be achieved through organized sub-decoders working together in iterations, resolving the contradiction by structuring complexity in a manageable nested fashion while maintaining high reliability.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent employs feedback mechanisms where decoded output from one iteration is re-encoded and fed back as reliability information to guide subsequent decoding iterations. The outer decoder's output is re-encoded to generate reliability metrics that inform the inner decoder's processing in the next iteration. This feedback loop enables progressive error correction refinement, improving reliability while managing complexity through iterative refinement rather than requiring all complexity to be present simultaneously.

Inventive Principle:
Principle #23Feedback

2Reliability

If concatenated decoding with interleaver is used, then burst error correction is improved, but processing time increases

Engineering Contradiction:
Improveburst error correctionVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent segments the error correction process into distinct functional blocks: an outer Reed-Solomon decoder handling burst errors at the block level, an interleaver that redistributes bits to spread burst errors, and an inner Viterbi decoder handling convolutional decoding. This segmentation allows each component to specialize in specific error types, improving burst error correction efficiency. The segmented structure enables parallel processing potential and optimized processing paths, reducing overall processing time compared to a monolithic decoder.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary interleaving before the main decoding process to pre-distribute burst errors across multiple code blocks. By performing this bit reordering operation in advance, the system prepares the data structure to facilitate more efficient error correction during the actual decoding phase. This preliminary action transforms concentrated burst errors into scattered single-bit errors that are easier and faster to correct, reducing the computational burden and processing time during critical decoding operations.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3605851A1Iterative decoding using re-encoding between decoding stages
Publication Date: 2020.02.05 NXP BV
  • EP3605851A1 patent drawingFigure 1
  • EP3605851A1 patent drawingFigure 2
  • EP3605851A1 patent drawingFigure 3

AI summary

Aspects of the present disclosure are directed to decoding signals susceptible to communication errors. As may be implemented in accordance with one or more embodiments, an input signal is decoded (110) to produce a first decoded output, which is subsequently encoded (120), and error characteristics of the encoded first decoded output are assessed (130). The input signal is again decoded (140) (e.g., with a delay), using the encoded first decoded output and the assessed error characteristics thereof to assess a reliability characteristic of bits in the input signal. A second decoded output is then provided with errors corrected therein based on the assessed reliability characteristic.