Iterative Decoding Circuit Using Erasure Address Comparison
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Solution Overview
Problem
Existing iterative decoding circuits for concatenated codes, such as those used in digital video broadcasting, face challenges in achieving small-area implementations with improved error-correction capabilities, particularly in handling burst noise and error correction beyond the Shannon Limit.
Innovation Solution
An iterative decoding circuit comprising two concatenated decoding circuits and a comparator, where the first and second convolutional decoders perform decoding operations, and the comparator generates erasure address information by comparing their results, thereby enhancing error correction without requiring a Soft-Output Viterbi Algorithm (SOVA) decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Soft-Output Viterbi Algorithm (SOVA) decoder is used to generate log-likelihood ratios and predict erasure positions, then error correction capability is improved, but circuit area becomes large
Solution Approach 1:
The patent divides the decoding system into two separate concatenated decoding circuits (first and second), each with its own convolutional decoder and block decoder. This segmentation allows the system to obtain multiple decoding results without requiring a complex SOVA decoder, thereby reducing circuit area while maintaining error correction capability through comparison of the segmented decoding paths.
Solution Approach 2:
The patent creates a copy of the concatenated decoding circuit (second concatenated decoding circuit identical to the first) to generate an alternative decoding result. By comparing the original decoding result with this copied version, the system can identify erasure positions and improve error correction without the complexity of a SOVA decoder.
2Area of stationary object
If Reed-Solomon decoder corrects errors without erasure position information, then circuit area remains small, but error correction capability is limited to t errors
Solution Approach 1:
The patent introduces a comparator as an intermediary component that compares decoding results from two different concatenated decoding circuits. This comparator generates erasure position information that is then provided to the Reed-Solomon decoder, enabling the decoder to achieve enhanced error correction capability (2e+r≤2t) without increasing its own circuit area.
Solution Approach 2:
The system performs preliminary decoding operations through two separate concatenated decoding circuits before the final Reed-Solomon decoding stage. By pre-processing the data through multiple decoding paths and using the comparator to identify potential error positions in advance, the Reed-Solomon decoder receives helpful erasure information that enhances its correction capability without requiring the decoder itself to be complex.
Data Source
AI summary
An iterative decoding circuit is provided. The iterative decoding circuit includes a first concatenated decoding circuit, a second concatenated decoding circuit, and a comparator. The first concatenated decoding circuit includes a first convolutional decoder, a first deinterleaver, and a first block decoder. The second concatenated decoding circuit is coupled to the first concatenated decoding circuit, and the second concatenated decoding circuit includes a second convolutional decoder, a second deinterleaver, and a second block decoder. The comparator receives a first convolutional decoding result corresponding to a first convolutional decoding operation and a second convolutional decoding result of a second convolutional decoding operation, and is configured to compare the first convolutional decoding result with the second convolutional decoding result to generate a comparing result. The second block decoder obtains an erasure address information according to the comparing result.