Iterative Decoding Instructions for Lower-Power Vector Processing
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Solution Overview
Problem
Existing computer systems face challenges in efficiently performing iterative decoding operations, particularly in soft-decoding algorithms, due to complexity and high power consumption when implemented using dedicated circuits or general-purpose processors, leading to potential errors and performance limitations.
Innovation Solution
A modified instruction set architecture is introduced that includes specific instructions such as soft_xor, additive correction, and multiplicative correction commands, which simplify the iterative decoding process by combining multiple operations into a single instruction, reducing power consumption and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If iterative decoding operations are implemented using dedicated circuits or general-purpose processors, then the decoding function can be performed, but the complexity and power consumption increase significantly
Solution Approach 1:
The patent combines multiple decoding operations (soft-decoding, hard-decoding, and error detection) into a unified instruction set architecture that can be executed by general-purpose processor cores. This merging eliminates the need for separate dedicated decoding circuits while maintaining decoding functionality through standardized instructions that operate on vector data structures.
Solution Approach 2:
The instruction set architecture provides universal instructions that can perform both soft-decoding and hard-decoding operations, as well as error detection, using the same hardware resources. The vector-based instruction format allows these instructions to handle different data types and decoding modes without requiring specialized circuitry for each function.
2Reliability
If iterative decoding operations are implemented using dedicated circuits or general-purpose processors, then the decoding function can be performed, but power consumption increases
Solution Approach 1:
The patent merges multiple decoding stages and operations into a single integrated instruction execution flow. By combining soft-decoding iterations, hard-decoding, and error detection into one unified process executed by processor cores, the system eliminates redundant data transfers and separate processing stages, thereby reducing overall power consumption while maintaining decoding accuracy.
3Reliability
If multiple software instructions are used to perform iterative decoding operations, then the decoding can be performed, but the number of instructions increases complexity and reduces efficiency
Solution Approach 1:
The patent merges multiple sequential software instructions into single vectorized instructions that can perform multiple decoding operations simultaneously. The soft-decoding instruction, for example, can execute multiple iteration steps in parallel using vector operations, dramatically reducing the total instruction count and improving decoding efficiency while maintaining accuracy.
Solution Approach 2:
The patent transitions from scalar instruction execution to vector-based parallel execution by organizing decoding data into vector structures. This dimensional change allows the same instruction to operate on multiple data elements simultaneously, effectively performing multiple decoding iterations or operations in parallel, thereby improving productivity without sacrificing decoding accuracy.
Data Source
AI summary
A storage circuit is configured to store multiple vectors associated with variable and check nodes of an iterative decoding operation. As part of the iterative decoding operation, a processor circuit is configured to retrieve, from the storage circuit, an intermediate value vector, a first estimation vector, a second estimation vector, and a sign vector, and determine an absolute value of the intermediate value vector. The processor circuit is also configured, using the retrieved vectors, to generate updated values for the first and second estimation vectors as part of determining a bit estimate for a check node included in the iterative decoding operation.