Iterative Deep Learning Compiler Hierarchical Extraction
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Solution Overview
Problem
Conventional compilers are unable to efficiently optimize systems with various hierarchical structures, as they require different compiler code for each hardware hierarchy, limiting their ability to perform compilation and optimization across diverse hardware configurations.
Innovation Solution
A deep learning compiler that performs iterative compilation by extracting hierarchies from a target system and applying a common pass pipeline for graph-level, partitioning, scheduling, memory, and communication optimizations, using dialects such as graph, schedule, data movement, memory, and communication dialects, to generate a target executable binary applicable across different hardware architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional compilers are used for each hardware hierarchy, then optimization for specific hardware can be achieved, but device complexity and development difficulty increase significantly
Solution Approach 1:
The patent implements a universal deep learning compiler framework that can handle multiple hardware hierarchies (GPU, NPU, PIM) through a single codebase. The compiler uses hierarchical extraction to identify different levels of system organization and applies appropriate optimization passes at each level, eliminating the need for separate compiler implementations for different hardware types while maintaining effective optimization.
Solution Approach 2:
The patent segments the compilation process into distinct hierarchical levels (extracting hierarchies from the computational graph), where each level corresponds to a specific hardware organization level. This segmentation allows the compiler to apply targeted optimizations at each hierarchy level without overwhelming complexity, processing the computational graph through multiple passes that operate on progressively refined representations.
2Reliability
If separate compiler code is developed for each hardware configuration, then hardware-specific optimization is achieved, but adaptability to new hardware architectures is reduced
Solution Approach 1:
The patent implements a dynamic hierarchical extraction mechanism that automatically adapts to different hardware architectures by extracting relevant hierarchy levels from the computational graph based on the target hardware's organizational structure. This dynamic adaptation allows the same compiler framework to effectively optimize for diverse hardware configurations including GPUs, NPUs, and PIM systems without requiring pre-programmed knowledge of each specific architecture.
Solution Approach 2:
The universal compiler framework incorporates hardware-agnostic intermediate representations and optimization passes that can be configured for different hardware targets. The system maintains hardware-specific optimization capabilities through configurable pass pipelines that adapt to the target architecture while remaining part of a single unified compiler codebase.
3Reliability
If iterative compilation with multiple pass pipelines is implemented, then optimization quality improves, but compilation time increases
Solution Approach 1:
The patent performs preliminary hierarchical extraction and analysis of the computational graph before applying optimization passes. By pre-identifying the relevant hierarchy levels and data flow patterns, the compiler prepares the graph structure in advance, enabling subsequent optimization passes to operate more efficiently and reduce overall compilation time while maintaining high optimization quality.
Solution Approach 2:
The iterative compilation process implements continuous refinement through multiple passes that build upon each other's results. Each pass operates on the output of the previous pass, progressively improving the optimization quality without redundant re-analysis. This continuous action approach ensures that compilation time is spent productively at each stage, with each pass contributing to the final optimization result.
Data Source
AI summary
An electronic device includes a deep learning compiler configured to receive a hardware representation corresponding to a target system comprising a hierarchical structure, extract a plurality of hierarchies from the target system based on the received hardware representation, and perform iterative compilation on the plurality of extracted hierarchies.