Iterative ECC Decoding for Resistive and Flash Memory Errors
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Solution Overview
Problem
Existing error correction methods for resistive and flash memories face challenges with high bit error rates, leading to increased latency and footprint due to the use of powerful error-correcting codes.
Innovation Solution
A device and method that combines a correcting module to correct up to r−1 erroneous bits and a detecting module to check for errors, utilizing a smaller footprint and lower latency ECC decoder, with iterative decoding cycles to correct errors efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If powerful error-correcting codes are used to correct high bit error rates, then error correction capability is improved, but latency and footprint of the ECC decoder increase
Solution Approach 1:
The patent segments the error correction process into two distinct modules: a correcting module that handles up to r-1 erroneous bits using traditional ECC decoding, and a detecting module that identifies cases where r or more bits are erroneous by checking if syndrome-based error location identification succeeds. This segmentation allows the system to use simpler, faster correction for the majority case while only invoking more complex detection when needed, thereby reducing average latency while maintaining reliability.
Solution Approach 2:
The patent applies partial action by having the correcting module attempt correction for up to r-1 bits without fully committing to handling all possible error cases. The detecting module then provides excessive action by checking whether the partial correction was sufficient, enabling the system to stop early when fewer than r bits are erroneous, thus reducing average processing time while maintaining the ability to detect uncorrectable errors.
2Reliability
If powerful error-correcting codes are used to correct high bit error rates, then error correction capability is improved, but footprint of the ECC decoder increases
Solution Approach 1:
The patent segments the ECC decoder functionality into two separate modules with distinct responsibilities: the correcting module implements the core ECC decoding logic for correcting up to r-1 bits, while the detecting module adds minimal overhead to check for uncorrectable errors. This segmentation allows the footprint-optimizing aspects of the correcting module to be implemented efficiently, while the detecting module uses lightweight syndrome-based checks that require minimal additional hardware resources.
Solution Approach 2:
The patent uses copying in the sense that the detecting module reuses the syndrome calculation and error location identification logic already present in the correcting module, rather than implementing completely separate error detection and correction pathways. This reuse of existing computational structures minimizes the additional footprint required for error detection capability.
3Productivity
If traditional ECC decoding is used, then error correction is achieved, but it cannot handle cases where r or more bits are erroneous
Solution Approach 1:
The patent merges the correcting module and detecting module into a unified error correction system where both functions operate cooperatively. The correcting module handles the primary error correction task for up to r-1 bits, while the detecting module is integrated to identify cases where r or more bits are erroneous. This merging ensures that both correction and detection capabilities work together seamlessly, maintaining high productivity while improving reliability for cases exceeding the traditional correction limit.
Solution Approach 2:
The detecting module provides feedback to the overall system about whether the number of erroneous bits exceeds the correction capability of r-1. When the detecting module determines that r or more bits are erroneous (by finding that error location identification fails or produces inconsistent results), it signals this condition back to the system, enabling appropriate error handling while allowing the correcting module to continue operating efficiently for correctable cases.
Data Source
AI summary
An error correction in resistive memories or flash memories protected by an error-correcting code is provided. A device makes it possible to correct at least two erroneous bits per code word stored in memory and combines a correcting module capable of correcting up to r−1 erroneous bits per code word, and a detecting module makes it possible to check the number of erroneous bits per code word, and is arranged to detect whether the read code word contains at most r−1 erroneous bits. If it does not, a sequence of decoding operations is initiated on a succession of words, each of which contains a single inverted bit with respect to the read code word. A check is carried out to check whether the number of erroneous bits in the version of the code word with inversion of one bit has become correctable in order to correct the code word.