Iterative Error Correction With Dynamic Reliability Bit-Precision
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Solution Overview
Problem
Error correction devices operating with predetermined bit-precision face limitations in accurately reflecting reliability information during decoding operations, leading to reduced error correction performance due to hardware complexity and increased power consumption.
Innovation Solution
The error correction device employs variable node units and check node units that receive and update hard decision bits based on channel reliability values and check reliability values, upsizing bit-precision to enhance decoding performance through iterative operations and the use of upsizing and downsizing tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit-precision of the error correction device is increased, then error correction performance is enhanced, but hardware complexity and power consumption increase
Solution Approach 1:
The patent implements dynamic bit-precision adjustment where the precision of reliability values is changed based on the decoding stage. During initial decoding iterations, lower precision (first bit-precision) is used, and during later iterations or critical updates, higher precision (second bit-precision) is applied. This dynamic switching allows the system to achieve high error correction performance when needed while maintaining lower hardware complexity during routine operations.
Solution Approach 2:
The patent changes the precision parameter of reliability values during the decoding process. The system maintains two different bit-precision levels and selectively applies them based on decoding requirements. This parameter change enables the device to optimize between accuracy and complexity by using appropriate precision levels for different operational contexts within the error correction process.
2Reliability
If bit-precision of the error correction device is increased, then error correction performance is enhanced, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the computational precision based on the decoding iteration stage and reliability requirements. By using lower precision during initial iterations and only switching to higher precision when necessary for accurate reliability updates, the patent reduces overall power consumption while maintaining error correction performance.
Solution Approach 2:
The patent applies higher bit-precision selectively only when and where it is truly necessary for accurate error correction, rather than uniformly across all operations. This partial application of high precision - specifically during critical reliability updates in variable node units - achieves the needed performance improvement without the full power cost of high-precision operation throughout the entire system.
3Device complexity
If predetermined bit-precision is used in the error correction device, then hardware complexity is reduced, but accuracy of reliability information reflection is limited
Solution Approach 1:
The patent implements a dynamic precision system that adapts the bit-precision of reliability values based on the decoding context. The system switches between first bit-precision (lower) and second bit-precision (higher) depending on whether accurate reliability information is critical for the current decoding step, thus achieving high measurement precision when needed without permanently increasing hardware complexity.
Solution Approach 2:
The system changes the precision parameter of reliability representations during operation. By maintaining multiple precision levels and selecting appropriate precision based on decoding stage and reliability importance, the patent achieves accurate reliability information reflection without the constant hardware overhead of high-precision arithmetic throughout the entire system.
Data Source
AI summary
An error correction device includes: a plurality of variable node units each configured to: receive a hard decision bit and a channel reliability value having a first bit-precision; and perform an iteration of a decoding operation on the hard decision bit based on the channel reliability value; a plurality of check node units each configured to: receive one or more reference reliability values having a second bit-precision from one or more variable node units coupled thereto among the plurality of variable node units during the iteration; and transmit, based on the one or more reference reliability values, one or more check reliability values having the second bit-precision to the one or more variable node units coupled thereto, wherein, during the iteration, each of the plurality of variable node units further: receives one or more first check reliability values from one or more check node units coupled thereto among the plurality of check node units; and updates the hard decision bit with reference to the channel reliability value and the one or more first check reliability values by upsizing the first bit-precision of the channel reliability value and the second bit-precision of the one or more first check reliability values.