Iterative FEC Decoding With Check Feedback for PS-QAM Signals

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

In the PS-QAM system, the lack of correlation between FEC decoding and PS decoding results in poor FEC decoding performance and reduced system transmission capability.

Innovation Solution

The receive end device performs level-M FEC decoding on the first bit signal, checks the resulting second bit signal to obtain a check result, and then performs level-(M+1) FEC decoding based on this check result, improving the accuracy of the third bit signal and enhancing FEC decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If separate FEC decoding and PS decoding are performed without correlation, then the decoding process is simple, but the FEC decoding performance deteriorates

Engineering Contradiction:
Improvedecoding process complexityVSAvoidFEC decoding performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent merges FEC decoding and PS decoding into a unified iterative decoding framework where the two decoding processes are correlated through mutual information exchange. The FEC decoder and PS decoder are combined to form an integrated decoding system that iteratively processes the received signal, allowing the check capability of PS decoding to enhance FEC decoding performance while maintaining manageable complexity through structured integration.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements feedback mechanisms where the check results from PS decoding are fed back to guide FEC decoding operations. The iterative process allows decoded information to be fed back between the FEC and PS decoding stages, with each iteration using the check results to improve the reliability of the decoded bit signal, thereby resolving the contradiction between simplicity and performance.

Inventive Principle:
Principle #23Feedback

2Measurement precision

If iterative FEC decoding with check results is performed, then the accuracy of decoded bit signal improves, but the decoding complexity increases

Engineering Contradiction:
Improveaccuracy of decoded bit signalVSAvoiddecoding process complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent employs dynamic iterative decoding where the decoding process adapts based on check results. The system dynamically adjusts the decoding iterations, performing level-M FEC decoding followed by checks, and conditionally proceeding to level-(M+1) decoding based on the first check result. This dynamic approach improves accuracy by only performing additional decoding when necessary, rather than always executing the full iterative process.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements partial iterative decoding where not all possible decoding levels are always executed. The system performs checks after level-M decoding and uses the check results to determine whether to proceed to level-(M+1) decoding. This partial action approach balances accuracy improvement with complexity control by performing only the necessary decoding iterations based on the actual quality of the received signal and intermediate decoding results.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP3869714B1Decoding method and decoding apparatus
Publication Date: 2025.04.16 HUAWEI TECH CO LTD
  • EP3869714B1 patent drawingFigure 1
  • EP3869714B1 patent drawingFigure 2A
  • EP3869714B1 patent drawingFigure 2B~4

AI summary

Embodiments of this application disclose a decoding method, so as to improve FEC decoding performance and a system transmission capability. The method according to the embodiments of this application includes: receiving, by a receive end device, a first bit signal; performing, by the receive end device, level-M forward error correction FEC decoding on the first bit signal to obtain a second bit signal, where M is a positive integer greater than zero; checking, by the receive end device, the second bit signal to obtain a first check result; performing, by the receive end device, level-(M+1) FEC decoding on the second bit signal based on the first check result to obtain a third bit signal; and performing, by the receive end device when M+1 reaches a first preset threshold, data processing on the third bit signal to obtain a fourth bit signal, where the fourth bit signal is used by the receive end device to obtain service data transmitted by a transmit end device.