Iterative Hard-Decision FEC Decoding With RS Feedback

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Solution Overview

Problem

Existing decoding systems for ATSC-encoded digital television signals face inefficiencies in error detection and correction, particularly due to the complexity of soft-decision decoding of Reed-Solomon codes, which is an NP problem and limits performance near the Shannon limit.

Innovation Solution

A hard-decision RS-based iterative decoding scheme is employed, utilizing factor graph circuitry and convolutional deinterleaver circuitry to restore symbol ordering and correct errors, with algorithms like Berlekamp-Massey and Euclidean for syndrome calculation and error correction, and Viterbi for trellis decoding, to achieve improved decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If soft-decision decoding of Reed-Solomon codes is used, then error detection and correction performance is improved, but computational complexity increases significantly

Engineering Contradiction:
Improveerror detection and correction performanceVSAvoidcomputational complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The decoding process is segmented into two distinct stages: first, hard-decision decoding of the Reed-Solomon codes is performed to correct symbol errors; second, the corrected hard decisions are fed back to the trellis decoder for additional error correction. This segmentation allows the system to achieve performance close to soft-decision decoding while avoiding the prohibitive computational complexity of direct soft-decision RS decoding.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of performing soft-decision decoding directly on the Reed-Solomon codes (the conventional approach), the patent inverts the approach by first making hard decisions on the RS codes and then using those hard decisions as feedback to the trellis decoder. This inversion allows the system to achieve similar error correction performance with significantly reduced complexity.

Inventive Principle:
Principle #13The other way round (Inversion)

2Device complexity

If hard-decision decoding is used for Reed-Solomon codes, then computational complexity is reduced, but error detection and correction performance deteriorates

Engineering Contradiction:
Improvecomputational complexityVSAvoiderror detection and correction performance
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the hard-decision output from the Reed-Solomon decoder is fed back to the trellis decoder. This feedback allows the trellis decoder to use the corrected hard decisions to improve its own decoding, effectively compensating for the performance loss that would normally occur with hard-decision decoding. The iterative feedback process enables the system to achieve performance close to the Shannon limit while maintaining low computational complexity.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7617435B2Hard-decision iteration decoding based on an error-correcting code with a low undetectable error probability
Publication Date: 2009.11.10 TAMIRAS PER PTE LTD LLC
  • US7617435B2 patent drawing
  • US7617435B2 patent drawing
  • US7617435B2 patent drawing

AI summary

A decoding system decodes forward error correction (FEC) encoded data. Factor graph circuitry (such as trellis decoder circuitry) processes the FEC encoded data according to at least one factor graph. Order restoring circuitry (such as convolutional deinterleaver circuitry) is coupled to an output of the factor graph circuitry and restores ordering of symbols in the encoded data. Error detection and correction circuitry is coupled to an output of the order restoring circuitry and processes block-based error correcting codes to detect and correct errors in the FEC encoded data and to provide a hard-decision output to an output of the decoding system. Feedback circuitry (such as convolutional interleaver circuitry and symbol interleaver circuitry) is coupled to process the hard-decision output from the error correction and detection circuitry and to provide the processed hard-decision output to the factor graph circuitry.