Iterative Validation of Machine-Readable Instructions

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Solution Overview

Problem

Computing devices with additional processors lack a hardware root of trust to validate machine-readable instructions, leading to potential compromises and errors due to the absence of a secure validation mechanism for these processors.

Innovation Solution

Implementing an iterative validation process using the main processor to validate machine-readable instructions for additional processors, which involves multiple iterations with random selection of instruction subsets and comparison with expected values stored securely, ensuring the integrity of firmware executed by these processors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If machine-readable instructions are executed on additional processors without validation, then processing capability is improved, but security and reliability deteriorate due to potential compromises

Engineering Contradiction:
Improveprocessing capabilityVSAvoidsecurity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs preliminary validation of machine-readable instructions before execution on additional processors. The main processor validates instructions by comparing them against stored validation criteria, ensuring security is established before productivity-generating operations commence.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The main processor acts as an intermediary between the untrusted additional processors and the system's secure operations. It validates instructions intended for additional processors, mediating the trust relationship and preventing direct execution of unvalidated code.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If an iterative validation process is implemented, then security and reliability are improved, but device complexity increases due to multiple validation iterations

Engineering Contradiction:
Improveintegrity verificationVSAvoidvalidation process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The validation process is segmented into multiple independent iterations, each validating a different subset of instructions. This divides the complex validation task into manageable segments that can be processed separately and combined for comprehensive verification.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The validation system dynamically adapts by performing multiple iterations with varying parameters. Each iteration may use different validation subsets or criteria, making the process flexible and robust rather than rigid and static.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11269637B2Validating machine-readable instructions using an iterative validation process
Publication Date: 2022.03.08 HEWLETT PACKARD ENTERPRISE DEV LP
  • US11269637B2 patent drawing
  • US11269637B2 patent drawing
  • US11269637B2 patent drawing

AI summary

In some examples, a system includes a first processor, a second processor, and a storage medium to store first information comprising machine-readable instructions executable by the second processor. The first processor is to validate the machine-readable instructions using an iterative validation process involving a plurality of iterations at different times, where each respective iteration of the plurality of iterations includes issuing a respective indication to the second processor to compute a value based on a respective subset of the first information, wherein the respective indication includes respective subset information identifying the respective subset, wherein the respective subset information differs from different subset information included in another indication issued in another iteration of the plurality of iterations, the different subset information identifies a different subset of the first information. Each iteration further includes determining a validity of the machine-readable instructions based on the value returned to the first processor by the second processor.