Iterative LDPC Decoding with Partition Multiplexing Across Code Lengths
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Solution Overview
Problem
Existing decoder designs face inefficiencies and increased costs when supporting error correcting codes with vastly different block lengths, as separate decoders for each length require significant silicon area and lead to suboptimal code selection, while multiplexing codes becomes inefficient when block lengths vary significantly.
Innovation Solution
A flexible decoding method using time-division multiplexing of decoding logic allows a single decoder to efficiently process multiple block lengths by spreading the decoding of larger codewords into multiple time slots without compromising error correction performance, enabling the use of optimal LDPC codes for different block lengths with reduced time to market and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate decoders are used for each code length, then decoding performance is optimized for specific block lengths, but silicon area increases significantly
Solution Approach 1:
The patent implements a universal decoder architecture that can handle multiple LDPC code lengths (512, 1024, 2048, 4096 bits) using the same hardware resources. The decoder uses configurable parameters including number of processing units, iterations, and time slots that can be adjusted to optimize performance for different code lengths, eliminating the need for separate dedicated decoders for each length.
Solution Approach 2:
The decoder employs dynamic configuration where the number of processing units, iterations, and time slots can be adjusted based on the required code length. This dynamic adaptability allows the same hardware to efficiently decode various code lengths by reconfiguring operational parameters, achieving both area efficiency and decoding performance optimization.
2Area of stationary object
If multiplexing codes in the decoder is used, then silicon area is reduced, but efficiency decreases when block lengths vary significantly
Solution Approach 1:
The patent segments the decoding process into multiple time slots and uses multiple processing units that can be dynamically allocated. The LDPC code is divided into syndromes processed in parallel by different processing units across multiple time slots, allowing efficient handling of various code lengths without sacrificing decoding efficiency.
Solution Approach 2:
The decoder changes operational parameters such as the number of processing units activated, number of iterations, and time slot allocation based on the input code length. This parameter adaptation maintains high decoding efficiency across different block lengths while using the same underlying hardware architecture.
3Adaptability or versatility
If multiplexing codes in the decoder is used, then code support is increased, but decoder complexity increases due to lack of fine speed control
Solution Approach 1:
The universal decoder supports multiple LDPC code lengths (512, 1024, 2048, 4096 bits) through a single configurable architecture. By using the same processing units with adjustable parameters (number of units, iterations, time slots), the decoder achieves versatile code support without requiring separate hardware for each code length, thereby avoiding increased complexity.
Data Source
AI summary
Examples relate to a decoding apparatus, a decoding device, a decoding method, a decoding computer program, and a communication device, a memory device and a storage device comprising such a decoding apparatus or decoding method. A decoding apparatus for performing iterative decoding on a codeword comprises processing circuitry comprising a plurality of processing units, and control circuitry configured to control the iterative decoding of the codeword. The iterative decoding is based on a parity-check matrix. The matrix is sub-divided into two or more partitions. The control circuitry is configured to operate in a first mode of operation to process a codeword having a first length, and to operate in a second mode of operation to process a codeword having a second length. The control circuitry is configured to multiplex the utilization of the plurality of processing units across the two or more partitions of the matrix at least in the second mode of operation.