Memory Error Correction Using Iterative LDPC-RS Syndrome Updates
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Solution Overview
Problem
Existing memory systems face inefficiencies in error correction due to the sequential processing of inner and outer error correction codes, leading to prolonged correction times and reduced reliability.
Innovation Solution
A memory system employing an iterative correction method that combines LDPC and RS codes, where a syndrome is generated and updated during the correction process, allowing for simultaneous C1 and C2 code corrections without re-reading data from non-volatile memory, thereby simplifying the error correction process and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential error correction processing using C1 code and C2 code is performed, then error correction capability is improved, but correction time becomes long
Solution Approach 1:
The patent combines C1 and C2 error correction operations into a unified iterative correction process. The correction unit performs both C1 correction (using first parity data) and C2 correction (using second parity data) in an integrated manner, allowing simultaneous processing of both error correction codes rather than sequentially executing them separately.
Solution Approach 2:
The patent implements dynamic iterative correction where the correction unit repeatedly alternates between C1 and C2 correction operations until convergence is achieved. This dynamic approach adapts the number of correction iterations based on the actual error conditions in the read data, allowing the system to terminate early when corrections are successful rather than always completing a fixed number of iterations.
2Reliability
If iterative correction between C1 and C2 codes is performed, then error correction capability is improved, but processing complexity increases
Solution Approach 1:
The patent segments the error correction process into distinct functional units: a correction unit that performs C1 and C2 corrections, a syndrome calculation unit that computes syndromes for error detection, and a determination unit that decides when to terminate iteration. This modular segmentation manages complexity by organizing the iterative process into manageable, specialized components with clear interfaces.
Solution Approach 2:
The patent implements feedback mechanisms where syndromes are calculated after each correction iteration and used to determine whether further correction is needed. The determination unit uses syndrome values as feedback to decide termination, creating a closed-loop control system that automatically adjusts the number of iterations based on actual correction needs, thereby managing processing complexity through intelligent feedback-based termination.
3Reliability
If multiple error correction codes are used, then data reliability is improved, but data transfer volume increases
Solution Approach 1:
The patent designs the correction unit to perform multiple functions: it can execute C1 correction using first parity data, C2 correction using second parity data, and both corrections in an iterative combined manner. This multi-functional unit processes different types of correction operations within a single hardware/software module, reducing the need for separate dedicated processing paths and minimizing overall data transfer requirements.
Solution Approach 2:
The patent introduces syndromes as intermediary data structures that mediate between the raw read data and the correction operations. Instead of directly transferring and processing all parity data multiple times, the syndrome calculation unit computes compact syndrome values that capture error information, which then guide the iterative correction process. This intermediary representation reduces the volume of data that needs to be transferred and processed repeatedly.
Data Source
AI summary
A memory system includes a non-volatile memory and a controller. The controller is configured to perform iterative correction on a plurality of frames of data read from the non-volatile memory. The iterative correction includes performing a first error correction on each of the frames including a first frame having errors not correctable by the first error correction, generating a syndrome on a set of second frames that include the first frame, performing a second error correction on the second frames using the syndrome, and performing a third error correction on the first frame. Each of the frames includes user data and first parity data used in the first error correction, the first parity data of the first frame also being used in the third error correction.