Iterative Memory Write Interfaces for Precision Control
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Solution Overview
Problem
Current memory interfaces and methods for nonvolatile memory (NVM) systems lack improvements to enhance operational efficiency, particularly in converging on target states during write operations and ensuring accurate data storage across various memory types.
Innovation Solution
The implementation of advanced interfaces and methods involving iterative write operations, where a controller and memory device interface use differential pairs for analog or digital signals, with iterative programming pulses to converge on target states, ensuring accurate data storage and retrieval across different memory types like NAND Flash, PCM, and MRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If iterative write operations are implemented to converge on target states, then write operation precision is improved, but operation time increases
Solution Approach 1:
The patent applies preliminary action by performing read operations before write operations to determine the current state of memory cells. This preliminary assessment allows the system to pre-calculate the appropriate programming pulses needed, reducing the number of iterative cycles required to reach target states and thereby decreasing total operation time while maintaining precision.
Solution Approach 2:
The patent implements feedback mechanisms where read operations continuously monitor the state of memory cells during iterative write operations. This feedback allows the system to adjust subsequent programming pulses dynamically, converging faster on target states by eliminating unnecessary iterations and reducing overall operation time while preserving write precision.
2Measurement precision
If differential pairs are used for analog or digital signals, then data transmission accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the differential pair interface to handle both analog and digital signal modes within the same hardware structure. This multi-functionality allows the system to achieve high data transmission accuracy through differential signaling while avoiding the need for separate dedicated circuits for each signal type, thereby reducing overall device complexity.
Solution Approach 2:
The patent implements dynamics by allowing the differential pair interface to dynamically switch between analog and digital operating modes based on the specific memory device being accessed and the operation requirements. This adaptability enables the system to optimize for accuracy when needed while simplifying operations when possible, balancing data transmission accuracy with device complexity management.
3Reliability
If iterative programming pulses are applied to memory cells, then data storage reliability is improved, but energy consumption increases
Solution Approach 1:
The patent applies partial action by determining the minimum number of programming pulses required to achieve reliable data storage based on preliminary read operations and state assessment. Rather than applying a fixed excessive number of pulses to all cells, the system tailors the pulse count to each cell's specific needs, ensuring data storage reliability while minimizing unnecessary energy consumption from redundant pulsing.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the characteristics of programming pulses (amplitude, duration, timing) based on the current state of memory cells and the target state requirements. This adaptive approach allows the system to achieve reliable data storage with optimized energy expenditure by using stronger pulses when needed and weaker pulses when sufficient progress has been made, rather than applying uniform high-energy pulses to all cells.
Data Source
AI summary
Controllers, interfaces, memory devices, methods and systems are disclosed, including a controller configured to interface with a separate memory device and perform an iterative write operation to program a selected memory cell of the memory device to a target state, wherein each iteration of the write operation is configured to successively change a physical state of the selected memory cell. Other controllers, interfaces, memory device, methods and systems are also described, such as those where either a controller or a memory device can throttle a data communication operation, and/or those that utilize customized programming pulses.