Iterative Multiplicative Reduction Circuit for Cryptographic Processing

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Solution Overview

Problem

Existing integrated circuits, including CPUs and FPGAs, are inefficient in performing large-scale modular multiplication operations required for cryptographic and blockchain applications, leading to slow processing speeds and high power consumption.

Innovation Solution

An iterative modular multiplication circuit that performs modular multiplication and reduction in parallel, using a multi-cycle implementation and overclocking with error checking, allowing for simultaneous operation of multiplicative expansion and division reduction, and employing a multi-level clocking scheme to enhance throughput and reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional CPU or FPGA implementations are used for modular multiplication, then flexibility is maintained, but processing speed is slow and power consumption is high

Engineering Contradiction:

Improveprocessing speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The circuit segments the modular multiplication operation into distinct phases: multiplicative expansion phase and division reduction phase. Each phase is handled by dedicated circuitry operating in parallel, with the expansion circuit computing partial products while the reduction circuit simultaneously performs modular reduction operations. This segmentation enables higher throughput without proportionally increasing power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The circuit employs a multi-cycle implementation where different phases of the computation are executed in periodic cycles. The expansion and reduction operations are interleaved across multiple clock cycles, allowing the circuit to maintain high arithmetic efficiency while managing power consumption through structured periodic operation patterns.

Inventive Principle:

Principle #19Periodic action

2Productivity

If iterative multiplicative reduction is performed in parallel, then arithmetic efficiency increases, but circuit complexity increases

Engineering Contradiction:

Improvearithmetic efficiencyVSAvoidcircuit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The circuit merges the expansion and reduction operations into a unified iterative architecture where both operations proceed in parallel within the same computational framework. This integration allows the circuit to achieve high arithmetic efficiency while managing complexity through a cohesive design that reuses computational resources across both phases.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The circuit employs dynamic operation modes where the expansion and reduction phases can be independently controlled and adjusted. The multi-cycle implementation allows flexible timing and resource allocation, enabling the circuit to adapt its operational characteristics to balance arithmetic efficiency with circuit complexity management.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS20230273770A1Iterative Multiplicative Reduction Circuit

Publication Date: 2023.08.31 ALTERA CORP

AI summary

Integrated circuit devices, methods, and circuitry for implementing and using an iterative multiplicative modular reduction circuit are provided. Such circuitry may include polynomial multiplication circuitry and modular reduction circuitry that may operate concurrently. The polynomial multiplication circuitry may multiply a first input value to a second input value to compute a product. The modular reduction circuitry may perform modular reduction on a first component of the product while the polynomial multiplication circuitry is still generating other components of the product.