Iterative Signal Processing with Timing-Error Computation Skipping
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Solution Overview
Problem
Existing digital signal processing systems face challenges in maintaining constant throughput and avoiding throughput penalties due to timing errors, especially when operating beyond critical voltage or frequency limits, leading to unacceptable output quality and increased power consumption.
Innovation Solution
A signal processing device employing a computation-skip scheme that detects timing errors and adjusts the number of computation iterations based on a control signal, allowing for operation beyond critical conditions by skipping iterations to ensure timely data arrival, thus maintaining a fixed cycles per instruction (CPI) without throughput penalty.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the supply voltage and clock frequency are scaled beyond the critical point to improve performance and reduce power consumption, then speed and power efficiency are improved, but timing errors occur leading to unacceptable output quality
Solution Approach 1:
The patent implements a feedback mechanism where timing monitors continuously monitor the timing slack in the circuit. When timing violations are detected (negative timing slack), the system generates timing error signals that trigger error correction schemes. This closed-loop feedback allows the system to operate beyond the critical voltage/frequency point while maintaining output quality by dynamically detecting and correcting timing errors.
Solution Approach 2:
The patent uses on-chip timing monitors to predictively detect potential timing violations before they result in incorrect output. By monitoring timing slack in advance and generating early warnings of impending timing errors, the system can take corrective action (such as inserting wait states or adjusting operational parameters) before the timing error propagates to the output, thus maintaining reliability while allowing aggressive voltage/frequency scaling.
2Productivity
If on-chip timing monitors are embedded to reduce design margin and enable operation beyond critical points, then performance capability is improved, but device complexity increases
Solution Approach 1:
The patent extracts the timing monitoring function from the main computational logic into separate, dedicated timing monitor circuits. These monitors are integrated into the existing circuit architecture but operate independently to detect timing violations. By separating the monitoring function from the computational function, the patent reduces the complexity impact on the main logic while still enabling performance improvements through aggressive scaling.
3Reliability
If error correction schemes are implemented to correct timing errors, then output quality is maintained, but throughput is reduced due to extra computation cycles
Solution Approach 1:
The patent implements a computation-skip scheme where, upon detecting a timing error, the system skips the erroneous computation iteration and proceeds directly to the next valid iteration. Instead of executing redundant correction cycles, the system rushes through the error by bypassing the problematic computation entirely. This approach maintains output quality by excluding erroneous results while minimizing throughput penalty by avoiding extra computation cycles.
Data Source
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AI summary
The present invention relates to an error resilient scheme for a signal processing device (100) arranged for performing an iterative processing on a clocked input data (Q) and for outputting an output data (O), the signal processing device (100) comprising: a computation circuit (20) comprising at least one computation unit circuit (21) arranged for performing one computation in each iteration on said clocked input data (Q) and for outputting a processed data (C1), and a selection circuit (30) arranged for outputting as said output signal (O) either said processed data (C1) or said clocked input data (Q), depending on a control signal (Ctrl) representative of a set-up timing error detected in an input data (D).