ITO Interlayer Wiring for LCD Scan Signal Resistance
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Solution Overview
Problem
The existing wiring structures in liquid crystal display devices have high connection resistance between scan lines and signal lines due to the length of the ITO layer required for connection, which is not adequately reduced by conventional through-hole configurations.
Innovation Solution
The arrangement of scan line and signal line through-holes in a matrix or staggered comb shape configuration allows for a shorter ITO connection length, reducing the resistance between the scan lines and signal lines by using intercrossed or staggered through-holes that engage like combs, facilitating a more efficient electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-holes are arranged to directly connect scan lines and signal lines, then connection resistance is reduced, but photolithography processes increase and manufacturing complexity increases
Solution Approach 1:
The patent introduces an ITO layer as an intermediary material to connect scan lines and signal lines. Instead of directly drilling through-holes to connect the lines, the ITO layer is deposited to fill the through-holes and establish electrical connection. This mediator approach reduces the complexity of direct through-hole connection while maintaining electrical connectivity.
Solution Approach 2:
The patent performs preliminary actions by forming through-holes on scan lines and signal lines separately before filling them with ITO layer. This staged approach allows for better control of the manufacturing process and reduces the complexity of simultaneous direct connection requirements.
2Device complexity
If ITO layer is used to connect scan lines and signal lines, then photolithography processes are reduced, but connection resistance increases due to ITO layer resistance
Solution Approach 1:
The patent applies local quality by optimizing the ITO layer properties specifically at the connection regions between scan lines and signal lines. The ITO layer is deposited with controlled thickness and composition to achieve low resistance at critical connection points while maintaining overall manufacturing simplicity.
Solution Approach 2:
The patent changes parameters of the ITO layer such as thickness, composition, and deposition conditions to optimize its electrical conductivity. By adjusting these parameters, the connection resistance through the ITO layer is minimized while maintaining the advantage of reduced photolithography processes.
3Reliability
If the length of ITO layer between scan line and signal line is reduced, then connection resistance is reduced, but through-hole arrangement complexity increases
Solution Approach 1:
The patent utilizes dimensional changes by arranging through-holes in specific three-dimensional configurations. The through-holes are positioned and oriented to create optimal pathways for the ITO layer, reducing the effective connection length while managing the spatial arrangement complexity through strategic positioning in multiple dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces the connection resistance between scan lines and signal lines, improving the electrical connectivity and manufacturing efficiency while maintaining cost-effectiveness by minimizing the photolithography processes.
Implementation Method 1
a transparent electrode layer electrically connecting the scan lines and the signal lines via the signal line layer through-holes and the scan line layer through-holes
Data Source
AI summary
A substrate for display device is provided. As a wiring structure of the substrate, the scan line layer and the signal line layer are not connected directly by arranging through-holes between the scan line layer and the signal line layer, but are connected through an ITO layer by arranging through-holes between the scan line layer and the ITO layer and arranging through-holes between the signal line layer and the ITO layer, with an object to reduce the value of the connection resistance between the scan line layer and the signal line layer. Through-holes connecting the scan line layer and the ITO layer and through-holes connecting the signal line layer and the ITO layer are configured in a comb shape respectively and engaged with each other. Thus the length of the ITO connecting the scan line layer and the signal line layer becomes shorter and the value of the connection resistance is reduced.