ITTAGE Branch Prediction Using Tagged Pattern Tables

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Solution Overview

Problem

Current Target Address Predictors in pipelined microprocessor architectures face challenges in accurately predicting indirect branch targets, leading to performance delays and increased hardware costs due to the need for extensive pattern caches.

Innovation Solution

A unified Indirect Target TAgged GEometric (ITTAGE) design is implemented, utilizing a target address pattern table to enhance prediction accuracy by tracking tagged history patterns and indexing into existing ITTAGE tables, thereby reducing hardware requirements while maintaining performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If extensive pattern caches are used to improve indirect branch target prediction accuracy, then prediction accuracy is improved, but hardware cost increases

Engineering Contradiction:
Improveprediction accuracyVSAvoidhardware cost
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The predictor is divided into multiple TAGE tables with different history lengths (e.g., 4 tables with history lengths of 2, 4, 6, and 8 bits). Each table handles a specific segment of the prediction task, allowing the system to achieve high accuracy without requiring a single large, expensive pattern cache. The segmentation enables efficient use of hardware resources by distributing the prediction workload across multiple smaller tables.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If extensive pattern caches are used to improve indirect branch target prediction accuracy, then prediction accuracy is improved, but hardware usage increases

Engineering Contradiction:
Improveprediction accuracyVSAvoidhardware usage
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The TAGE predictor implements a nested structure where multiple tables with different history lengths are organized hierarchically. The tables are nested in the sense that they share common indexing mechanisms and tag structures, with each table building upon the previous ones. This nesting allows the system to achieve comprehensive pattern matching capability while minimizing hardware usage through shared resources and incremental history processing.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Device complexity

If traditional target address predictors are used, then hardware implementation is simpler, but prediction accuracy decreases leading to performance delays

Engineering Contradiction:
Improvehardware implementation simplicityVSAvoidperformance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The TAGE predictor dynamically adapts to different branch patterns by selectively using entries from multiple tables with varying history lengths. The predictor dynamically adjusts which table entries are consulted based on the current branch instruction's characteristics, allowing it to optimize between simplicity and accuracy in real-time. This dynamic approach enables the system to maintain relatively simple hardware while achieving high prediction accuracy through adaptive selection of prediction sources.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10261797B2Indirect target tagged geometric branch prediction using a set of target address pattern data
Publication Date: 2019.04.16 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10261797B2 patent drawing
  • US10261797B2 patent drawing
  • US10261797B2 patent drawing

AI summary

Provided is a method for predicting a target address using a set of Indirect Target TAgged GEometric (ITTAGE) tables and a target address pattern table. A branch instruction that is to be executed may be identified. A first tag for the branch instruction may be determined. The first tag may be a unique identifier that corresponds to the branch instruction. Using the tag, the branch instruction may be determined to be in a target address pattern table, and an index may be generated. A predicted target address for the branch instruction may be determined using the generated index and the largest ITTAGE table. Instructions associated with the predicted target address may be fetched.