Integrated Voltage Regulator Chiplet Layout for Scalable Power Delivery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional integrated voltage regulators (IVRs) in microelectronic assemblies face scalability issues due to the inclusion of analog circuits, which prevents them from being reduced in size as other on-die logic circuits scale, leading to increased area usage and power delivery challenges in multi-die IC packages.
Innovation Solution
The implementation of a microelectronic assembly with a chiplet that includes a capacitor and a switching transistor or diode, integrated between the package substrate and the die, allowing for more flexible design, reduced size, and improved power delivery by decoupling the IVR components from the main die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If conventional IVR includes analog circuits on the same die, then power delivery function is achieved, but area usage increases and scalability is prevented
Solution Approach 1:
The patent segments the IVR into separate components: the control logic is integrated on the die while the power delivery circuitry (analog circuits, capacitors, inductors) is placed on separate chiplets or external components. This segmentation allows the die area to be minimized while maintaining full power delivery functionality through the distributed architecture.
Solution Approach 2:
The patent transitions from a two-dimensional planar integration of all IVR components on a single die to a three-dimensional stacked architecture using chiplets connected via through-silicon vias (TSVs). This vertical stacking enables power delivery components to be positioned in additional spatial dimensions, reducing the footprint on the main die while maintaining functional integration.
2Power
If conventional IVR includes analog circuits on the same die, then power delivery function is achieved, but scalability is prevented
Solution Approach 1:
By segmenting the IVR into modular components (control logic on die, power delivery on separate chiplets), the system becomes scalable. Different configurations of chiplets can be selected and combined based on specific power delivery requirements, allowing the same die architecture to be adapted across multiple product generations and applications.
Solution Approach 2:
The patent creates a universal die architecture with standardized interfaces that can work with various chiplet configurations. The control logic die serves multiple functions across different applications, while the power delivery capabilities are scaled by selecting appropriate chiplet combinations, achieving both universality and adaptability.
3Power
If IVR components are integrated on the die, then power delivery is achieved, but package size increases
Solution Approach 1:
The patent implements a nested architecture where chiplets containing power delivery components are placed within or adjacent to the main die package. The chiplets are vertically stacked using TSVs, creating a compact nested structure that minimizes the overall package volume while maintaining all necessary power delivery functions.
Solution Approach 2:
The patent utilizes the vertical dimension through 3D stacking of chiplets connected by TSVs, transforming the package from a spread-out 2D layout to a compact 3D structure. This vertical integration dramatically reduces the package footprint and overall volume while maintaining full power delivery functionality.
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.