Finite-Field JAM Error Correction for Memory Read Reliability
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Solution Overview
Problem
Existing error correction schemes in memory devices either lack sufficient error correction capability or require complex and resource-intensive computations, making them impractical for efficient implementation.
Innovation Solution
Implementing a Jenkinson adjusted magnitude (JAM) error correction scheme using a finite field to generate position and magnitude error correction bits, allowing for simple logic operations to correct errors in memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction schemes are used, then error correction capability is limited, but implementing more complex math to increase correction capability requires impractical number of logic gates
Solution Approach 1:
The patent changes the mathematical parameters used in error correction by employing Jenkinson adjusted magnitude arithmetic over a finite field instead of traditional binary arithmetic. This allows the system to achieve higher error correction capability (correcting up to 3 bit errors) while using a manageable number of logic gates by redefining how corrections are calculated and applied.
Solution Approach 2:
The patent substitutes complex traditional error correction mathematics with a simplified arithmetic system based on finite field theory and Jenkinson adjusted magnitude operations. This replacement reduces the computational complexity and logic gate requirements while maintaining or improving error correction performance.
2Reliability
If more error correction capability is implemented, then data integrity improves, but the complexity of math required becomes impractical
Solution Approach 1:
The patent transforms the mathematical parameters by operating within a finite field structure where arithmetic operations are modular and bounded. This parameter change enables the system to handle more errors (improving data integrity) while keeping the math manageable through finite field properties rather than requiring impractical complex calculations.
Solution Approach 2:
The patent segments the error correction process into distinct components: position error correction bits indicating where errors occur, and magnitude error correction bits indicating how to correct them. This segmentation allows the complex task of correcting multiple bit errors to be broken down into simpler, more manageable operations.
3Ease of manufacture
If simplified logic operations are used, then implementation becomes practical, but error correction capability may be reduced
Solution Approach 1:
The patent changes the arithmetic parameters to finite field-based operations that can be implemented with relatively simple logic circuits. By redefining how corrections are computed using modular arithmetic and finite field properties, the system achieves both simplicity in implementation and sufficient error correction capability without requiring overly complex hardware.
Data Source
AI summary
A memory device includes a Jenkinson adjusted magnitude (JAM) error correction circuit. The JAM error correction circuit converts data into symbols in a finite field, and then generate magnitude and error correction bits from those symbols. During a read operation, the JAM error correction circuit generates an error magnitude based, in part, on the magnitude error correction bits and generates an error position based, in part, on the position error correction bits. The JAM error correction corrects the symbol at the location specified by the error position by an amount specified by the error magnitude. The use of the finite field may help simplify the logic operations compared to other multi-bit error correction schemes.