JESD204-to-PCIe Interface Conversion Module
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Solution Overview
Problem
The existing methods for connecting Joint Electron Devices Engineering Council (JESD)204 and Peripheral Component Interconnect Express (PCIe) interfaces are inefficient due to differences in physical layers, encoding, scrambling, and modulation schemes, leading to complex and costly solutions with high latency.
Innovation Solution
A method is provided to seamlessly and synchronously connect JESD204 interfaces with PCIe interfaces by transceiving JESD204 link layer messages and converting between JESD204 and PCIe scrambled/encoded messages, using a conversion module that operates at the respective clock rates and physical layers, thereby bypassing the need for expensive glue logic and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs and memory elements are used to decouple JESD204 and PCIe interfaces, then interface compatibility is achieved, but device complexity and BOM cost increase
Solution Approach 1:
The patent merges the JESD204 and PCIe interface protocols into a unified conversion module that performs protocol translation, encoding conversion, and clock domain crossing in a single integrated structure. This eliminates the need for separate FPGAs and memory elements, directly reducing device complexity while maintaining interface compatibility.
Solution Approach 2:
The conversion module is designed to handle multiple functions simultaneously: protocol conversion between JESD204 and PCIe, encoding transformation (64b/66b to 128b/130b), scrambling/descrambling operations, and clock domain crossing. This multi-functional approach replaces multiple discrete components with a single universal interface solution.
2Adaptability or versatility
If FPGAs and memory elements are used to decouple JESD204 and PCIe interfaces, then interface compatibility is achieved, but BOM cost increases
Solution Approach 1:
The patent merges the JESD204 and PCIe interface protocols into a unified conversion module that performs protocol translation, encoding conversion, and clock domain crossing in a single integrated structure. This eliminates the need for separate FPGAs and memory elements, directly reducing device complexity while maintaining interface compatibility.
Solution Approach 2:
The patent replaces expensive, complex FPGA-based solutions with a more economical integrated conversion module that can be implemented using standard semiconductor manufacturing processes. This approach uses cost-effective components and architectures while achieving the same interface compatibility function.
3Adaptability or versatility
If FPGAs and memory elements are used to decouple JESD204 and PCIe interfaces, then interface compatibility is achieved, but data transmission speed decreases
Solution Approach 1:
The patent extracts the clock domain crossing function from traditional memory-based approaches and implements it directly within the conversion module using synchronous design techniques. This eliminates the latency introduced by memory read/write operations and achieves near-real-time protocol conversion without speed degradation.
Solution Approach 2:
The conversion module acts as an intelligent intermediary between JESD204 and PCIe interfaces, performing real-time protocol translation and data transformation without the need for intermediate storage in memory. This direct conversion approach eliminates the speed bottleneck created by memory access latency while maintaining data integrity.
4Adaptability or versatility
If additional memory and connections are added to resolve JESD204/PCIe mismatch, then interface compatibility is achieved, but device complexity increases
Solution Approach 1:
The patent merges the JESD204 and PCIe interface protocols into a unified conversion module that performs protocol translation, encoding conversion, and clock domain crossing in a single integrated structure. This eliminates the need for separate FPGAs and memory elements, directly reducing device complexity while maintaining interface compatibility.
Solution Approach 2:
The patent resolves the interface mismatch by operating in the protocol conversion dimension rather than adding physical layers. The conversion module translates JESD204 protocols into PCIe protocols through systematic data transformation, avoiding the need for additional physical connections or memory interfaces while achieving full compatibility.
Data Source
AI summary
A system and method are provided for interfacing JESD204-to-PCIe communications. The method transceives JESD204 link layer messages with a JESD204 link layer. The method converts between JESD204 link layer messages and PCIe scrambled messages. The method converts between PCIe scrambled messages and PCIe encoded messages. The PCIe encoded messages are transceived at a JESD clock rate. The PCIe encoded messages transceived at the JESD clock rate are buffered and PCIe encoded messages are then transceived at a PCIe clock rate. The PCIe encoded messages at the PCIe clock rate are transceived with a PCIe physical layer. That is, PCIe encoded messages are either transmitted to the PCIe physical layer at the PCIe clock rate (the transmission path), or received from the PCIe physical layer (at the PCIe clock rate) and buffered (the receive path). The system and method also enable conventional JESD link layer-to-JESD physical layer communications.