JESD204B Link Delay Control via Lane Segmentation
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Solution Overview
Problem
The JESD204B interface standard poses challenges in aligning multiple data lanes and ensuring link delay, particularly due to stringent hardware and board-level wiring requirements, which increase design complexity and cost in wireless communication systems.
Innovation Solution
The method involves performing frequency division on the Local Multi Frame Clock (LMFC) of each data lane to obtain a second LMFC, writing data into a buffer, and generating a third LMFC based on a SYSREF signal and preset interval to read data, easing the delay processing restrictions and reducing clock frequency complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the JESD204B interface protocol limit is applied (processing delay cannot exceed one LMFC length), then link delay is controlled, but design complexity and hardware requirements increase greatly
Solution Approach 1:
The patent segments the delay control into two independent parts: write delay control (using write valid signals and write addresses for each lane) and read delay control (using read valid signals and read addresses for each lane). This segmentation allows each lane to be configured independently while maintaining overall synchronization, reducing the complexity compared to controlling all lanes with a single unified delay mechanism.
Solution Approach 2:
The patent applies preliminary action by pre-configuring write valid signals and write addresses before data writing, and pre-configuring read valid signals and read addresses before data reading. This allows the system to prepare delay parameters in advance for each lane, enabling flexible delay adjustment without requiring complex real-time delay calculation and control mechanisms.
2Adaptability or versatility
If the LMFC length is increased to accommodate larger delay differences, then delay tolerance is improved, but clock frequency complexity increases
Solution Approach 1:
The patent implements dynamic delay adjustment by allowing each lane to have independently configurable write valid signals, write addresses, read valid signals, and read addresses. This dynamic configuration capability enables the system to adapt to different delay requirements of each lane without requiring a fixed, overly conservative LMFC length, thus avoiding unnecessary clock frequency complexity while maintaining adequate delay tolerance.
Solution Approach 2:
The patent changes the parameters of delay control from a fixed LMFC-length-based approach to a flexible parameter-based approach using write valid signals, write addresses, read valid signals, and read addresses for each lane. This parameter change allows precise control of each lane's delay characteristics without being constrained by the minimum 17-byte LMFC length requirement, reducing clock frequency complexity while improving adaptability.
3Reliability
If multiple data lanes are aligned using traditional methods, then signal integrity is maintained, but board level wiring complexity increases
Solution Approach 1:
The patent segments the data lane handling into independent write and read operations for each lane, with each lane having its own write valid signal, write address, read valid signal, and read address. This segmentation allows each lane to be processed independently through the buffer, reducing the need for complex synchronized wiring between lanes while maintaining signal integrity through controlled memory access operations.
Solution Approach 2:
The patent introduces a buffer as an intermediary between the data lanes and the processing system. The buffer mediates the data transfer by accepting data from multiple lanes with different delays and providing synchronized output. This intermediary approach eliminates the need for complex board-level wiring to synchronize lanes, as the buffer internally manages the timing and synchronization, simplifying the physical wiring requirements while maintaining signal integrity.
Data Source
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AI summary
The disclosure provides a method for determining link delay. The method includes: according to a preset frequency division multiple, performing frequency division on a first Local Multi Frame Clock (LMFC) of each data lane obtained by parsing to obtain a second LMFC corresponding to each data lane, and, according to the second LMFC, writing respectively the data of each data lane into a corresponding buffer; and according to a SYSREF signal and a preset LMFC interval, generating a third LMFC, and, according to the third LMFC, reading respectively the data of each data lane from the corresponding buffer. The period of the second LMFC is the same as the period of the third LMFC. The disclosure also provides an apparatus, a communication device and a storage medium for implementing the method.