Multi-transistor Memory Cell with JFET Access Gate
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory cells with high-K gate dielectrics, such as SHINOS memory transistors, face reliability issues despite improved program and erase characteristics, and existing SONOS memory cells suffer from retention problems due to direct tunnelling at low power.
Innovation Solution
A multi-transistor memory cell design featuring a metal gate-SHINOS memory transistor with a memory gate stack comprising a bottom dielectric layer, nitride charge trapping layer, top dielectric layer, metal layer, and poly silicon layer, along with an enhancement junction field effect transistor access transistor, which avoids high-K dielectrics and maintains memory cell size flexibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If high-K gate dielectrics (HfSiOx) are used in SHINOS memory transistors to reduce program and erase voltages, then program and erase characteristics are improved, but reliability problems occur
Solution Approach 1:
The invention segments the memory cell into two distinct transistors: a memory transistor with high-K gate dielectric (HfSiOx) for reliable charge storage, and a separate access transistor with conventional SiO2 dielectric for reliable switching operation. This segmentation allows each transistor to be optimized for its specific function, resolving the reliability issue by preventing the high-K dielectric from being used in the access transistor where it causes leakage problems.
Solution Approach 2:
The invention applies different dielectric materials to different locations within the memory cell: HfSiOx is used specifically in the memory transistor's gate stack where high-K properties are needed for low-voltage operation and good retention, while conventional SiO2 is used in the access transistor where reliability and low leakage are critical. This local differentiation resolves the contradiction by placing each material where it provides the most benefit without causing harm.
2Use of energy by stationary object
If SONOS memory cells operate with direct tunnelling at low power, then power consumption is reduced, but retention problems occur
Solution Approach 1:
The memory transistor uses a composite gate stack structure comprising multiple layers: bottom SiO2, charge trapping Si3N4, top SiO2, HfSiOx, and metal gate. This composite structure combines the tunnelling properties of SiO2/Si3N4 for charge storage with the high-K properties of HfSiOx for enhanced electric field control, achieving both low power operation and good retention through material composition rather than relying solely on direct tunnelling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides enhanced reliability and reduced program/erase voltages for memory cells, improving endurance and retention while maintaining cell size flexibility, thus addressing the reliability concerns of existing high-K dielectric and SONOS memory cells.
Implementation Method 1
the memory gate stack is arranged for storing electronic charge
Implementation Method 2
as such low power SONOS memory cells, operated by direct tunnelling, suffer from retention problems, high-K dielectrics in combination with metal gates are used to replace the silicon oxide layers
Implementation Method 3
SONOS memory cell devices, operated by direct tunnelling
Data Source
AI summary
The invention relates to a multi-transistor, e.g. a two-transistor memory cell with an enhancement junction field effect transistor (JFET) as the access gate transistor. In one embodiment, the JFET is provided as a self-aligned JFET. Accordingly, and advantageous over the prior art, the invention allows for a method for manufacturing a multi-transistor, e.g. a two-transistor memory cell comprising a JFET as the access transistor without adding any additional masks and/or processing steps. Such a multi-transistor, e.g. a two-transistor memory cell according to invention, provides an improved reliability.