Junction Field Effect Transistor With Balanced Electric Fields
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Solution Overview
Problem
Junction field effect transistors (JFETs) experience high gate current due to unbalanced electric fields, leading to impact ionization and increased noise, as current flows from the first channel region into regions where the electric fields from the top and bottom gates no longer balance.
Innovation Solution
The design balances electric fields by adjusting the relative geometries and dimensions of the device, such as the top-gate, bottom-gate, and drain, to direct current flow along a field-neutral path, using a 1:2 ratio for the channel width and depth, and a deep drain diffusion to separate the current from high electric fields, and employing polysilicon out-diffusion to reduce defects and noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the current flows from the first channel region into regions beyond the gate, then the current reaches the drain and source, but the unbalanced electric fields cause impact ionization and high gate current
Solution Approach 1:
The patent introduces a vertical dimension by implementing a back gate beneath the channel to counterbalance the horizontal electric field from the top gate. This two-dimensional gate configuration creates a field-neutral path that guides current flow away from high-field regions, reducing impact ionization and gate current while maintaining effective current transport from drain to source.
2Reliability
If the top gate is highly doped to reduce gate resistance and noise, then the gate resistance decreases, but the electric field from the top gate becomes stronger and unbalanced
Solution Approach 1:
The back gate serves as a counterweight to the top gate's electric field. By applying an opposing electric field from the back gate, the system balances the strong field from the highly doped top gate, creating a field-neutral environment that prevents impact ionization while allowing the top gate to maintain its low resistance properties.
3Object-affected harmful factors
If the channel depth is increased to separate current from high electric fields, then impact ionization is reduced, but the device dimensions and complexity increase
Solution Approach 1:
The back gate serves multiple functions simultaneously: it counterbalances the top gate's electric field, creates a field-neutral path for current flow, and effectively increases the channel depth without proportionally increasing device complexity. This multi-functional approach achieves field separation while maintaining manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces gate current and impact ionization, maintaining low electric fields along the current path, thereby minimizing noise and enhancing the performance of JFETs by aligning current flow with balanced electric fields and reducing high E-field regions.
Implementation Method 1
employing polysilicon out-diffusion to reduce defects and noise
Data Source
Figure 1
Figure 2
Figure 3a~3b
AI summary
A method of forming a junction field effect transistor, the transistor comprising: a back gate; a channel; a top gate; a drain and a source in current flow with the channel; wherein the method comprises selecting a first channel dimension between the top gate and the back gate such that a significant current flow path in the channel occurs in a region of relatively low electric field strength.