JFET Doping Gradient in Planar Power Transistors for Lower On-Resistance
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Solution Overview
Problem
The resistance of planar power transistors is significant due to the high resistance of the JFET region, which is a major component.
Innovation Solution
A semiconductor device design with a JFET region having a decreasing doping concentration and width away from the substrate, combined with shielding regions and well regions, forms a current spreading layer that reduces on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the JFET region has high doping concentration to reduce resistance, then the on-resistance decreases, but the device complexity increases due to the need for precise doping concentration gradients
Solution Approach 1:
The patent applies local quality by creating a doping concentration gradient within the JFET region, where the doping concentration varies from the substrate interface toward the drift layer. This gradient structure optimizes the resistance characteristics locally within different regions of the JFET, achieving lower on-resistance while maintaining manufacturability through controlled spatial variation of doping properties.
Solution Approach 2:
The patent implements parameter changes by systematically varying the doping concentration parameter across the JFET region depth. The doping concentration is highest at the substrate interface and decreases toward the drift layer, creating an optimized resistance profile that reduces on-resistance while the gradient nature simplifies the manufacturing process compared to uniform high-doping approaches.
2Reliability
If the JFET region width is reduced to lower resistance, then the on-resistance decreases, but the current carrying capacity is reduced
Solution Approach 1:
The patent applies local quality by creating distinct functional zones within the JFET region through the doping gradient. The higher doping concentration near the substrate provides low resistance pathways, while the gradual transition maintains adequate current carrying capacity across the device width. This spatial differentiation of doping quality allows simultaneous optimization of resistance and current capacity.
Solution Approach 2:
The patent transitions from considering only the horizontal width of the JFET region to incorporating the vertical depth dimension with doping concentration variation. By optimizing the doping profile through the depth of the JFET region rather than merely reducing the lateral width, the patent achieves lower on-resistance while preserving current carrying capacity through the additional dimensional degree of freedom.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design reduces on-resistance by allowing electron flow to spread over a larger area without restriction, aided by high-doping shielding regions forming a larger PN junction depletion region.
Implementation Method 1
a doping concentration of the junction field-effect transistor region decreases as being far away from the substrate
Implementation Method 2
high-doping shielding regions forming a larger PN junction depletion region
Data Source
AI summary
A semiconductor device includes a substrate, a drift layer, a junction field-effect transistor region, a well region, a source region, and a gate structure. The drift layer is over the substrate. The junction field-effect transistor region is over the drift layer, and a doping concentration of the junction field-effect transistor region decreases as being far away from the substrate. The well region is over the drift layer and at a side of the junction field-effect transistor region. The source region is in the well region. The gate structure is over the junction field-effect transistor region.