High Voltage JFET with Field Electrode Plate
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Solution Overview
Problem
Conventional JFETs have a limited breakdown voltage of 20-30 volts, restricting their application in high voltage fields, and there is a need for a high voltage JFET compatible with CMOS/LDMOS integrated circuit technology to meet emerging semiconductor requirements.
Innovation Solution
A high voltage JFET structure is developed with a channel on the surface of an epitaxial layer, employing the RESURF principle and drawing inspiration from LDMOS structures, which includes a field electrode plate extending to the surface of the drain terminal oxygen region, and adjustable pinch-off voltage through channel implantation conditions, ensuring compatibility with CMOS/LDMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional JFET structure with PN junction is used, then the device is simple to manufacture, but the breakdown voltage is limited to 20-30 volts
Solution Approach 1:
The device is segmented into multiple functional regions: a first conductivity type epitaxial layer, a second conductivity type drift region, a first conductivity type well region, and a second conductivity type channel layer. This segmentation allows each region to contribute to voltage bearing capability, with the breakdown voltage determined by the drift region and well region structure rather than being limited by a single PN junction.
Solution Approach 2:
The structure employs nested regions where the second conductivity type channel layer is formed within the first conductivity type well region, which itself is embedded in the second conductivity type drift region on the first conductivity type epitaxial layer. This nesting arrangement enables complex electric field control and voltage distribution to achieve high breakdown voltage while maintaining manufacturability.
2Reliability
If LDMOS structure with field electrode plate is used, then the breakdown voltage is improved, but the device cannot be applied to JFET due to different breakdown mechanism
Solution Approach 1:
The invention creates a universal structure that combines LDMOS high-voltage bearing features with JFET operation characteristics. The drift region and well region structure provides high breakdown voltage capability similar to LDMOS, while the channel layer configuration maintains JFET's field-effect control mechanism, making the structure adaptable to both device types.
Solution Approach 2:
Different regions of the device are assigned specific properties: the drift region provides high voltage bearing capability with low impurity concentration, the well region provides electric field control, and the channel layer provides carrier transport. This local differentiation of properties enables the device to achieve high breakdown voltage while maintaining JFET functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly enhances the breakdown voltage of the JFET to above 50 volts, making it suitable for high voltage applications while maintaining compatibility with existing CMOS/LDMOS integrated circuit production technology, and demonstrates good device performance with pinch-off voltage control.
Implementation Method 1
The pinch-off voltage of the high voltage JFET can be adjusted by controlling the implantation conditions of the channel implantation layer
Implementation Method 2
employing RESURF principle to greatly enhance a breakdown voltage of the JFET
Data Source
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AI summary
The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer. Wherein a drain electrode electrically is led out from the second conductivity type drain heavily doped region; a source electrode electrically is led out from a connection of the field electrode plate and the second conductivity type source heavily doped region; and a gate electrode electrically is led out from the first conductivity type gate heavily doped region. The transistor has a high breakdown voltage and easy to be integrated.