Half-Bridge JFET Gate Control to Cut Inverter Dead Time Losses
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Solution Overview
Problem
Conventional inverters with n-channel self-conducting junction field effect transistors (JFETs) experience dead time losses due to reverse conduction in the 3rd quadrant, necessitating a dead time to prevent short circuits, which increases power loss and requires larger chip areas.
Innovation Solution
A circuit arrangement with a half-bridge configuration using JFETs, controlled by a control unit to apply a dead time voltage during switching operations, reducing the dead time losses by maintaining the switch in an off state through a gate voltage below its threshold, dynamically adapting to boundary conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dead time is introduced to prevent short circuit during switching, then reliability is improved, but power loss increases due to reverse conduction in the 3rd quadrant
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the gate voltage of the JFET during the dead time period. Specifically, a negative voltage is applied to the gate to reduce the reverse conduction current in the 3rd quadrant, thereby reducing power loss while maintaining reliable short circuit prevention. This transforms the fixed switching behavior into a dynamically controlled process that optimizes both reliability and energy efficiency.
2Loss of energy
If dead time voltage control is implemented to reduce power loss, then energy efficiency is improved, but device complexity increases
Solution Approach 1:
The patent introduces an intermediary control mechanism within the driver unit that generates the appropriate dead time voltage based on switching signals. This intermediary component processes the control signals and applies the necessary gate voltage adjustments during dead time, achieving power loss reduction without requiring fundamental redesign of the entire inverter system. The intermediary approach isolates the complexity to a manageable control function.
3Device complexity
If conventional switching control is used, then device simplicity is maintained, but chip area increases due to higher power dissipation requirements
Solution Approach 1:
By changing the gate voltage parameter during dead time to reduce reverse conduction, the patent decreases power dissipation in the JFET. This reduced power dissipation allows for smaller heat sinking requirements and reduced chip area, as the device operates more efficiently during the critical dead time period when both switches are off.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces dead time losses and chip area by minimizing voltage drop in the 3rd quadrant, leading to lower power consumption and potential cost savings.
Implementation Method 1
A circuit arrangement with a half-bridge configuration using JFETs, controlled by a control unit to apply a dead time voltage during switching operations, reducing the dead time losses by maintaining the switch in an off state through a gate voltage below its threshold
Data Source
AI summary
A circuit arrangement for reducing dead time losses of an inverter and an electrical system. The circuit arrangement includes: a half-bridge arrangement including first and second switches; a load; a control unit; and a driver unit. The first switch is a junction field effect transistor. The half-bridge arrangement is for connection to a DC voltage source and provides an AC voltage to the load using complementary control of the first and second switches by the control unit based on a voltage of the DC voltage source. The control unit is configured to maintain a dead time between the complementary switching of the first and second switch. The driver unit is configured, based on a control by the control unit, to provide a gate of the first switch with a dead time voltage during a switch-on process and/or during a switch-off process of the first switch during the dead time.