JFET With Graded Channel Doping For Voltage Control
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Solution Overview
Problem
Conventional junction field effect transistors face limitations in modulating the channel cut-off voltage effectively, leading to potential breakdown in high-voltage devices due to high on-resistance and limited adjustability of the gate structure depth.
Innovation Solution
The proposed solution involves forming a junction field effect transistor with a substrate having high-voltage well regions and a channel region with a lower dopant concentration, achieved through thermal diffusion or counter-doping, allowing for effective modulation of the channel cut-off voltage without breaking down the gate structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate structure depth is increased to reduce channel cut-off voltage, then the channel cut-off voltage is reduced, but the gate structure and channel region break down before the channel is cut-off
Solution Approach 1:
The patent applies local quality by creating a graded doping concentration profile in the channel region, where the dopant concentration varies spatially. Specifically, the channel region has a lower dopant concentration than the high-voltage well regions, creating a localized property distribution that enables the channel to be pinched off at lower voltages without compromising the overall structural strength and breakdown characteristics of the device.
2Reliability
If the channel concentration is reduced by lowering down the drain concentration, then the channel cut-off voltage is reduced, but the on-resistance of the high-voltage device increases
Solution Approach 1:
The patent implements local quality through spatially varying dopant concentrations in different regions. The channel region is designed with lower dopant concentration to facilitate easy pinch-off and reduce cut-off voltage, while the high-voltage well and drain regions maintain higher dopant concentrations to preserve low on-resistance and high voltage handling capability. This localized differentiation resolves the contradiction between reducing cut-off voltage and maintaining low on-resistance.
Solution Approach 2:
The patent segments the device into distinct functional regions with different doping characteristics: the channel region segmented from the high-voltage well and drain regions. This segmentation allows independent optimization of each region's properties - the channel region for low cut-off voltage through lower doping, and the drain/high-voltage well regions for low on-resistance through higher doping, thereby resolving the technical contradiction.
3Strength
If the gate structure depth is decreased to prevent breakdown, then the channel cut-off voltage increases beyond the endurable range
Solution Approach 1:
The patent applies parameter changes by modifying the dopant concentration parameter in the channel region rather than changing the gate structure depth. By reducing the dopant concentration in the channel region relative to the high-voltage well regions, the patent achieves lower channel cut-off voltage without altering the gate depth, thereby maintaining structural strength while achieving the desired electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the channel cut-off voltage while preventing high-voltage device breakdown, enabling more precise control over the channel pinch-off and maintaining device reliability.
Implementation Method 1
performing an annealing process on the substrate to diffuse the dopant of the high-voltage well regions, thereby forming a channel region between the pair of high-voltage well regions
Implementation Method 2
implanting the substrate to form a pair of high-voltage well (HVW) regions beneath source/drain predetermined regions. The pair of high-voltage well regions have a dopant of a first conductive type
Data Source
AI summary
A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.