JFET and High Voltage Transistor Shared Deep-Well Segmentation
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Solution Overview
Problem
High voltage transistors and junction field effect transistors (JFETs) face challenges in minimizing size and controlling current-voltage characteristics due to the use of deep-well regions as both drift drain regions, making it difficult to optimize the on-resistance and pinch-off voltage.
Innovation Solution
A semiconductor device and manufacturing method that forms a JFET gate region in the channel width direction on a first conductivity type deep-well region, allowing for independent control of the pinch-off feature of the junction transistor while maintaining the electric features of the high voltage transistor, by using a buried impurity layer and a groove in the diffusion region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a deep-well region is used as both drift drain region of high voltage transistor and channel region of junction transistor, then area is reduced, but independent control of current-voltage characteristics becomes difficult
Solution Approach 1:
The patent segments the deep-well region into two distinct regions: a drift drain region for the high voltage transistor and a channel region for the junction transistor. This segmentation allows independent doping concentration control in each region, enabling separate optimization of on-resistance for the high voltage transistor and pinch-off voltage for the junction transistor, while still sharing the same physical deep-well structure to minimize area.
2Reliability
If doping concentration of deep-well region is determined according to on-resistance of high voltage transistor, then on-resistance is optimized, but pinch-off voltage control of junction transistor becomes difficult
Solution Approach 1:
The patent applies local quality by creating different doping concentration profiles in different spatial regions of the deep-well. The drift drain region has a doping concentration optimized for low on-resistance of the high voltage transistor, while the channel region has a doping concentration optimized for the pinch-off voltage of the junction transistor. This local differentiation allows each transistor to achieve its optimal electrical characteristics independently.
3Adaptability or versatility
If separate formation of high voltage transistor and junction transistor is used, then independent control is achieved, but area increases significantly
Solution Approach 1:
The patent merges the formation of the high voltage transistor and junction transistor by having them share the same deep-well region physically, while maintaining separate doping regions within that deep-well. This combining approach reduces the total device area by over 90% compared to separate formation, while still achieving independent control of electrical characteristics through the segmented doping structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the area usage by over 90% compared to separate formation of high voltage and junction transistors, enabling effective control of pinch-off voltage and current, thus improving integration and reducing power loss.
Implementation Method 1
a second conductivity type buried impurity layer which is located on the deep-well region
Implementation Method 2
a diffusion region having an impurity concentration that is lower than other portions of the deep-well region
Data Source
AI summary
The present examples relate to a junction field effect transistor (JFET) that shares a drain with a high voltage field effect transistor. The present examples are able to control a pinch-off feature of the junction transistor while also maintaining electric features of the high voltage transistor by forming a groove on a lower part of a first conductivity type deep-well region located on a channel region of the junction transistor in a channel width direction.