JFET Isolation Layout for High-Voltage, Low-Capacitance ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
JFET transistors face limitations in high-frequency performance due to stray capacitances between the drain, source, and gate regions, which restrict their application in supporting high voltages.
Innovation Solution
The integration of isolating regions and surface-diffused connection regions in the semiconductor substrate reduces stray capacitances by isolating the drain and source regions from the gate and channel regions, allowing for high-voltage support with minimized capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If source and drain regions are deeply diffused in the semiconductor substrate to support high voltage, then high voltage resistance is improved, but stray capacitances between drain/source regions and gate region increase, degrading high-frequency performance
Solution Approach 1:
The patent divides the semiconductor substrate into distinct regions separated by isolating regions. The source and drain regions are segmented from the gate region through these isolating structures, allowing each region to be optimized independently - source/drain regions can be deeply diffused for high voltage support while the gate region remains isolated to minimize stray capacitances.
Solution Approach 2:
Isolating regions are introduced as intermediary structures between the source/drain regions and the gate region. These isolating regions act as mediators that electrically separate the deeply diffused source/drain regions from the gate region, preventing direct capacitive coupling while allowing both regions to maintain their required depth and function.
2Strength
If source and drain regions are deeply diffused to support high voltage, then high voltage resistance is improved, but device complexity increases due to the need for additional isolating regions and connection structures
Solution Approach 1:
The isolating regions serve multiple functions simultaneously: they electrically isolate the source/drain regions from the gate region to reduce stray capacitances, they provide mechanical support for the deeply diffused regions, and they define the boundaries for subsequent processing steps. This multi-functionality reduces the need for additional separate structures.
Solution Approach 2:
The patent merges the isolation function with the region definition function into a single isolating region structure. Rather than adding separate isolation structures to already-formed deeply diffused regions, the isolating regions are formed as integral part of the region definition process, combining multiple functions into one structural element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances high-frequency performance and enables JFET transistors to support high voltages while reducing stray capacitances, allowing for improved performance in applications previously limited by capacitance issues.
Implementation Method 1
These deeply diffused regions have the drawback of creating stray capacitances between the drain region and the gate region, and between the source region and the gate region
Implementation Method 2
a first connection region connecting the drain region to the channel region while bypassing the first isolating region, and a second connection region connecting the source region to the channel region while bypassing the second isolating region
Data Source
AI summary
An integrated circuit includes a junction field-effect transistor formed in a semiconductor substrate. The junction field-effect transistor includes a drain region, a source region, a channel region, and a gate region. A first isolating region separates the drain region from both the gate region and the channel region. A first connection region connects the drain region to the channel region by passing underneath the first isolating region in the semiconductor substrate. A second isolating region separates the source region from both the gate region and the channel region. A second connection region connects the source region to the channel region by passing underneath the second isolating region in the semiconductor substrate.