Vertically Integrated JFET-MOS Transistor for Low Noise and Area Efficiency
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Solution Overview
Problem
Integrated circuits (ICs) face challenges in minimizing area while achieving low noise and high current density switching, as existing transistors either consume significant space or compromise on signal-to-noise ratios.
Innovation Solution
A vertically integrated transistor combining a JFET and an MOS transistor with shared source and drain nodes but independently controlled gates, compatible with common IC fabrication processes, allowing for both n-channel and p-channel versions without increasing fabrication cost or complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If JFET and MOS transistors are integrated to provide both low noise operation and high current density, then signal-to-noise ratio and current switching capability are improved, but IC area consumption increases significantly
Solution Approach 1:
The patent combines JFET and MOS transistor structures into a single integrated device that shares common source and drain regions. The JFET portion provides low noise operation for high signal-to-noise ratio requirements, while the MOS portion provides high current density switching capability. By merging these two transistor types into one structure with shared terminals, the patent achieves both low noise and high current density performance without requiring separate discrete transistors, thereby reducing the overall IC area compared to using separate JFET and MOS devices.
Solution Approach 2:
The patent implements a nested structure where the JFET and MOS transistor regions are vertically and laterally integrated within a shared substrate area. The JFET channel and MOS channel are positioned to share common source and drain regions, with independently controlled gates positioned above their respective channels. This nesting approach allows both transistor types to occupy overlapping or adjacent spatial regions, maximizing area utilization and reducing the total footprint compared to separate implementations.
2Adaptability or versatility
If separate JFET and MOS transistors are used to cover different operating ranges, then current switching capability is improved, but device complexity and fabrication process complexity increase
Solution Approach 1:
The patent creates a universal transistor structure that incorporates both JFET and MOS functionality within a single device. The shared source and drain regions serve both transistor types, while independently controlled gates allow the device to operate in different modes (JFET mode or MOS mode) depending on which gate is activated. This multi-functional design eliminates the need for separate JFET and MOS transistor fabrication processes, as both transistor types are created using the same process sequence, thereby reducing fabrication process complexity while maintaining versatility across different operating ranges.
3Area of stationary object
If vertically integrated transistor structure is implemented, then IC area is reduced, but fabrication process complexity may increase
Solution Approach 1:
The patent segments the transistor structure into distinct JFET and MOS regions that are vertically and laterally integrated but fabricated using sequential, independent process steps. The fabrication process is divided into stages: first forming the JFET structure with its channel and gate, then adding the MOS structure with its channel and gate in subsequent steps. This segmentation of the fabrication process into modular stages allows each transistor type to be created using standard process techniques without requiring complex simultaneous patterning, thereby reducing overall fabrication complexity while achieving area reduction through vertical integration.
Data Source
AI summary
Analog ICs frequently include circuits which operate over a wide current range. At low currents, low noise is important, while IC space efficiency is important at high currents. A vertically integrated transistor made of a JFET in parallel with an MOS transistor, sharing source and drain diffused regions, and with independent gate control, is disclosed. N-channel and p-channel versions may be integrated into common analog IC flows with no extra process steps, on either monolithic substrates or SOI wafers. pinchoff voltage in the JFET is controlled by photolithographically defined spacing of the gate well regions, and hence exhibits low variability.