JFET p-floating region ESD protection
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Solution Overview
Problem
High voltage junction field effect transistors (JFETs) face challenges in protecting against electrostatic discharge (ESD) surges, particularly the Human Body Model (HBM+) which exceeds 1000V, as existing methods either complicate the process, increase costs, or enlarge the chip size, while also affecting the cutoff current and voltage stability.
Innovation Solution
Incorporating a p-floating region with a higher impurity concentration on the surface of the n-drift region, electrically floating and separated from the source and drain regions, to enhance ESD capacity without increasing device size or reducing the cutoff current, along with a polysilicon resistor element for improved voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick insulating layer is formed on the high-voltage JFET and an ESD protection element is provided on this insulating layer, then ESD protection capacity is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent merges the ESD protection function with the existing JFET structure by forming a p-type floating region directly within the n-type drift region of the JFET. This integration eliminates the need for separate ESD protection elements and thick insulating layers, thereby improving ESD protection capacity while avoiding increased device complexity and manufacturing cost.
Solution Approach 2:
The p-type floating region serves multiple functions: it provides ESD protection capacity, maintains voltage distribution, and preserves the normal operation of the JFET. This multi-functionality allows a single structural modification to address ESD protection without requiring additional components or process steps.
2Reliability
If an ESD protection element is formed separately from the high voltage JFET, then ESD protection is improved, but chip size increases
Solution Approach 1:
The ESD protection function is merged into the existing JFET structure by forming the p-type floating region within the n-type drift region. This integration ensures that ESD protection is achieved without increasing chip size, as the protection mechanism shares the same physical space as the normal JFET operation regions.
3Reliability
If the n-drift region resistance is increased to divide ESD surge voltage, then ESD capacity is improved, but cutoff current decreases
Solution Approach 1:
The patent applies local quality by forming a p-type floating region with higher impurity concentration at a specific location within the n-type drift region. This localized modification creates a depletion region that provides ESD protection through voltage division, while the rest of the n-type drift region maintains its original properties to ensure sufficient cutoff current flows to the power supply capacitor.
Solution Approach 2:
The patent changes the impurity concentration parameter locally by forming a p-type floating region with higher impurity concentration within the n-type drift region. This parameter change creates a depletion region that provides ESD protection while maintaining the overall electrical characteristics of the JFET, including the cutoff current required for normal operation.
4Reliability
If the p-gate region impurity concentration is lowered to increase source breakdown voltage, then ESD capacity is improved, but cutoff voltage increases and control circuit operation becomes unstable
Solution Approach 1:
The patent applies local quality by forming a p-type floating region with higher impurity concentration at a specific location within the n-type drift region, rather than lowering the impurity concentration of the p-gate region. This localized modification provides ESD protection through depletion region formation while maintaining the p-gate region's electrical characteristics, thereby preserving voltage stability and ensuring stable control circuit operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively improves ESD capacity to at least 2000V without enlarging the device size or decreasing the cutoff current, maintaining voltage stability and operational efficiency.
Implementation Method 1
When a surge voltage is inputted, a depletion region is formed in the n-drift region 4 from the p-gate region 2, and a part of the surge voltage is divided by this depletion region.
Implementation Method 2
The pn junction 19 of the n-source region 3 and the p-gate region 2 is reverse biased, causing a depletion region to spread
Data Source
AI summary
In a high voltage JFET, a p-floating region is provided in the surface layer of an n-drift region, thereby increasing the resistance R of the n-drift region and minimizing the voltage divided at a pn junction. This makes it possible to improve ESD capacity without increasing device size and without making the cutoff current smaller.