JFET Structure with P-Substrate Gates for Low Noise
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Solution Overview
Problem
Manufacturing junction field effect transistors (JFETs) with standard CMOS procedures is costly and complex due to the need for carefully tailored implants to achieve correct channel depth, and without a buried gate, JFETs require several hundred volts to 'pinch off' the channel, leading to inefficiencies and high flicker noise.
Innovation Solution
The development of a JFET structure using N-tip channels and multiple gates, where the p-substrate acts as additional gates, allowing for effective control of current flow without a buried gate, reducing 1/f noise and eliminating the need for high voltages by creating a reverse bias region within the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If carefully tailored implants are used to achieve correct channel depth in JFET manufacturing, then manufacturing precision is improved, but device complexity and manufacturing cost increase due to additional masking steps
Solution Approach 1:
The p-substrate automatically forms depletion regions that act as gates to control the n-type channel, eliminating the need for separately formed gate structures. The substrate itself provides the gating function through its inherent p-type doping, self-regulating the channel depth and current flow without requiring additional masking or implantation steps.
Solution Approach 2:
The p-substrate serves multiple functions simultaneously: it provides mechanical support, establishes the n-type channel through doping, and creates depletion regions that function as gates for current control. This multi-functionality eliminates the need for separate gate structures and simplifies the manufacturing process while maintaining precise channel control.
2Device complexity
If no buried gate is used in JFET structure, then device complexity is reduced, but pinch-off voltage increases to several hundred volts reducing efficiency
Solution Approach 1:
The invention changes the doping concentration parameters of the p-substrate to create highly effective depletion regions. By optimizing the p-type doping level and the n-type channel doping level, the depletion regions achieve sufficient width and charge density to control current flow at low voltages, eliminating the need for high pinch-off voltages while maintaining simple device structure.
3Speed
If JFET operates at high frequencies, then speed is improved, but flicker noise increases due to mobile charge interaction with oxide interface
Solution Approach 1:
The invention extracts the n-type channel from the oxide interface environment by forming it within the bulk semiconductor material, surrounded by p-type depletion regions. This removes the channel from proximity to oxide traps and interface states that generate flicker noise, while maintaining the high-frequency performance through efficient depletion region control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces 1/f noise and allows for efficient control of current flow with lower voltages, maintaining high performance without additional circuitry or complex manufacturing steps, while using existing CMOS processes.
Implementation Method 1
When the gate voltage is applied, a depletion region is created by pushing mobile carriers away from the channel and 'pinching off' the channel.
Implementation Method 2
Another type of FET, known as a JFET, utilizes a p-n junction as the gate.
Data Source
AI summary
A microelectric product and the method for manufacturing the product are provided. A source and drain are spaced from one another in a first direction and are connected to opposing ends of a channel to provide a set voltage. First and second gates are spaced from one another in a second direction surrounding a portion of the channel to allow for application and removal of a gate voltage. Application of the gate voltage repels majority carriers in the channel to reduce the current that conducts between the source and drain.