JFET Reduced Doping Region for Gate Current Control
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Solution Overview
Problem
Junction field effect transistors (JFETs), particularly N-channel devices, experience significant increases in gate current at high drain-source voltages due to impact ionization, which is not effectively managed by existing fabrication processes.
Innovation Solution
A modified doping process is implemented during the fabrication of JFETs, where a mask with additional apertures adjacent to the drain aperture creates a region of reduced doping extending towards the channel, thereby extending the depletion region and reducing electric field gradients, thus minimizing impact ionization and gate current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional doping process is used to form the drain region, then the fabrication process is simple and compatible with bipolar transistor processes, but the gate current increases significantly at high drain-source voltages due to impact ionization
Solution Approach 1:
The patent applies local quality by creating a region of reduced doping concentration specifically at the drain edge adjacent to the channel, while maintaining higher doping in other drain regions. This localized modification reduces the electric field gradient at the critical drain-channel interface, thereby minimizing impact ionization and reducing gate current without requiring a complete redesign of the doping process
Solution Approach 2:
The doping process is segmented into multiple stages: first forming the main drain region with standard doping, then performing a second doping step through a mask with restricted apertures to create the reduced doping region at the drain edge. This segmentation allows precise control over the doping profile in different drain regions, addressing the gate current issue without compromising overall device fabrication
2Reliability
If the drain doping concentration is uniformly high, then the drain region provides good electrical contact and current handling, but the electric field gradient at the drain-channel interface causes impact ionization and increased gate current
Solution Approach 1:
The patent changes the doping concentration parameter locally at the drain edge by performing a second doping step that adds dopant material only in specific regions through restricted apertures. This creates a graded doping profile where the doping concentration transitions from high in the bulk drain to lower at the drain-channel interface, reducing the electric field gradient and minimizing impact ionization effects
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the gate current from 10% to less than 5% of the drain current at high voltages, enhancing the transistor's breakdown voltage and input impedance, making it more suitable for electronic devices.
Implementation Method 1
cause the depletion region around the drain in a working transistor to become extended
Implementation Method 2
reduce impact ionization, and in turn reduce gate current
Data Source
AI summary
A junction field effect transistor having a drain and a source, each defined by regions of a first type of semiconductor interconnected by a channel, and in which a dopant profile at a side of the drain facing the channel is modified so as to provide a region of reduced doping compared to a body region of the drain. The region of reduced doping and the body region can be defined by the same mask and doping step, but the mask is shaped to provide a lesser amount and thus less depth of doping for the region of reduced doping.