Junction Field Effect Transistor With Schottky Junction For High Breakdown Voltage
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Solution Overview
Problem
Junction field effect transistors (JFETs) require higher breakdown voltage in certain applications, but existing designs fail to achieve this effectively.
Innovation Solution
A JFET design incorporating a substrate with a buried layer, well regions, and Schottky junctions, where the first well region has a Schottky junction between the gate and drain lead-out regions, isolated by an isolation structure, and a P-type island beneath the first well region, along with a manufacturing method involving ion implantation, epitaxial growth, and thermal annealing to form a depletion region for enhanced breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional JFET structure is used, then device simplicity is maintained, but breakdown voltage is insufficient
Solution Approach 1:
The device is segmented into multiple doped regions including P-type substrate, N-type drift region, P-type well region, and N-type source/drain regions. This segmentation creates distinct functional zones that enable high breakdown voltage through the P-N junction depletion regions while maintaining a systematic structure that doesn't overly complicate the device architecture
Solution Approach 2:
The P-type well region acts as an intermediary structure between the N-type drift region and N-type source/drain regions. This intermediary P-type region creates additional depletion regions that enhance breakdown voltage without requiring complete restructuring of the basic JFET architecture
2Reliability
If Schottky junction is added to increase breakdown voltage, then voltage withstand capability is improved, but manufacturing complexity increases
Solution Approach 1:
The Schottky junction is merged with the existing P-type well region structure. The metal contact is formed over the P-type well region, combining the Schottky barrier function with the existing doped region structure. This integration allows the Schottky junction to contribute to breakdown voltage enhancement without requiring completely separate manufacturing processes
Solution Approach 2:
The manufacturing process utilizes parameter changes in the metal deposition and thermal annealing steps to form the Schottky junction. By controlling the metal layer composition, deposition conditions, and annealing parameters, the Schottky barrier is created with appropriate characteristics to enhance breakdown voltage while using standard semiconductor fabrication techniques
3Reliability
If multiple doped regions are introduced to enhance breakdown voltage, then voltage withstand capability is improved, but device complexity increases
Solution Approach 1:
Different doped regions are introduced with specific local qualities: the P-type substrate provides bulk support, the N-type drift region is optimized for voltage blocking, the P-type well region creates depletion zones, and N-type source/drain regions provide low-resistance contacts. Each region has tailored doping concentration and depth to optimize its local function, achieving high breakdown voltage through localized optimization rather than uniform complexity throughout the device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively increases the breakdown voltage by depleting the N-type drift region through the Schottky junction and P-type island, improving voltage withstand capability without increasing photolithography costs.
Implementation Method 1
the first well region is provided with a Schottky junction on a surface thereof, the Schottky junction is located between the first gate lead-out region and the drain lead-out region
Implementation Method 2
takes advantage of the Schottky junction above the N-type well to form a depletion region in the N-type drift region of the N-type well, so as to deplete the drift region, thereby achieving an object of improving the breakdown voltage
Implementation Method 3
forming a buried layer in the substrate by ion implantation; forming a first well region and a second well region in the epitaxial layer by ion implantation and drive-in; forming a source lead-out region and a drain lead-out region in the first well region by ion implantation
Implementation Method 4
forming an epitaxial layer on the buried layer by epitaxy technology
Implementation Method 5
activating implanted ion by thermal annealing
Data Source
AI summary
The present invention relates to a junction field effect transistor. The junction field effect transistor comprises a substrate (10), a buried layer in the substrate, a first well region (32) and a second well region (34) that are on the buried layer, a source lead-out region (50), a drain lead-out region (60), and a first gate lead-out region (42) that are in the first well region (32), and a second gate lead-out region (44) in the second well region (34). A Schottky junction interface (70) is disposed on the surface of the first well region (32). The Schottky junction interface (70) is located between the first gate lead-out region (42) and the drain lead-out region (60), and is isolated from the first gate lead-out region (42) and the drain lead-out region (60) by means of isolation structures. The present invention also relates to a manufacturing method for a junction field effect transistor.