Integrated JFET Schottky Diode for High Breakdown Voltage
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Solution Overview
Problem
Conventional Schottky diodes in integrated circuits have low breakdown voltage and high reverse leakage due to image force barrier lowering, and attempts to address these issues by incorporating a depletion-mode LDMOS transistor increase the diode's footprint and production costs.
Innovation Solution
Integration of a tunable junction field-effect transistor (JFET) device within the Schottky diode that clamps or constricts the conduction path in a non-lateral direction, depleting the path to reduce reverse leakage and enhance breakdown voltage, without adding process steps or increasing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a depletion-mode LDMOS transistor device is placed in series with the Schottky diode to address low breakdown voltage and high reverse leakage, then the breakdown voltage is improved, but the footprint of the Schottky diode increases
Solution Approach 1:
The patent merges the Schottky diode and JFET device into a single integrated structure where the JFET is formed within the same semiconductor substrate as the Schottky diode. The JFET gate, source, and drain regions are integrated with the Schottky diode's electrode and conduction path, creating a unified device that improves breakdown voltage without increasing footprint.
Solution Approach 2:
The JFET device is nested within the Schottky diode structure. The JFET gate region is positioned below the conduction path, and the JFET source and drain regions are formed within the conduction path region, effectively nesting the transistor structure inside the diode's active area.
2Reliability
If a depletion-mode LDMOS transistor device is placed in series with the Schottky diode to address high reverse leakage, then the reverse leakage is reduced, but additional procedures are incorporated into the process flow, increasing production cost
Solution Approach 1:
The patent combines the formation of the JFET device with the existing Schottky diode fabrication process. The same implantation, deposition, and etching steps that create the Schottky diode structure also form the JFET gate, source, and drain regions, eliminating the need for separate transistor fabrication procedures.
Solution Approach 2:
The fabrication process is designed to serve multiple functions simultaneously. The implantation steps create both the Schottky barrier junction and the JFET doped regions; the deposition steps form both the Schottky electrode and the JFET gate electrode, making the process universally applicable to both device types.
3Ease of manufacture
If a silicide layer is formed over an n-type or p-type crystalline silicon area to create a Schottky barrier junction, then the Schottky diode is formed, but the breakdown voltage is low and reverse leakage is high due to image force barrier lowering
Solution Approach 1:
The JFET device acts as an intermediary element between the Schottky barrier junction and the external circuit. The JFET's depleted conduction path modulates the current flow through the Schottky junction, effectively controlling the diode's electrical characteristics and improving breakdown voltage while maintaining fabrication simplicity.
Solution Approach 2:
The patent changes the electrical parameters of the conduction path by introducing the JFET structure. The JFET gate voltage controls the depletion width in the conduction path, dynamically adjusting the resistance and enabling the device to operate at higher breakdown voltages than a conventional Schottky diode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated JFET device achieves low forward voltage drop, low reverse leakage, and high breakdown voltage while maintaining compatibility with existing fabrication processes, thus improving the performance of Schottky diodes without increasing production complexity or costs.
Implementation Method 1
The JFET devices are integrated to control, decrease or minimize the reverse leakage level of the disclosed Schottky diodes by depleting the conduction path
Implementation Method 2
Schottky diodes fabricated in CMOS process flows are typically formed with a silicide layer over an n-type or p-type crystalline silicon area. The resulting Schottky barrier junction has undesirably low breakdown voltage and high reverse leakage levels due to image force barrier lowering.
Data Source
AI summary
A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.