Self-Aligned JFET Structure for Low Flicker Noise in CMOS Image Sensors
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Solution Overview
Problem
Conventional Junction field-effect transistors (JFETs) face challenges in device scale shrinking due to device geometry and photolithography manufacturing operations, limiting their application in low flicker noise requirements, especially in CMOS image sensors where larger scale JFETs are not feasible.
Innovation Solution
A scale-shrinking JFET transistor design that utilizes a self-align source-drain technique surrounded by a shallow trench isolation (STI) structure, with a gate formed outside the STI area, allowing for a reduced device length of about one-fourth that of conventional JFETs and maintaining sufficient distance between the channel and the silicon/silicon oxide surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional JFET geometry and photolithography manufacturing operations are used, then manufacturing process is straightforward, but device scale shrinking is limited
Solution Approach 1:
The patent introduces a third dimension by forming the gate region at a different depth level than the source and drain regions. The gate region extends to a first depth level while source and drain regions are at a second depth level, allowing the channel to extend underneath the gate. This vertical dimensionality change enables significant device length reduction while maintaining manufacturing feasibility through standard photolithography processes.
Solution Approach 2:
The patent segments the device structure into distinct depth levels: the gate region is formed at a first depth level while source and drain regions are formed at a second depth level. This segmentation allows independent formation and optimization of each region, enabling the channel to extend underneath the gate and achieve shorter device lengths without complicating the manufacturing process.
2Object-affected harmful factors
If MOS transistors of large dimensions are used, then output noise level is reduced, but silicon area consumption increases
Solution Approach 1:
By extending the channel underneath the gate into the vertical dimension, the patent achieves better noise performance without increasing the lateral silicon area. The channel length is effectively increased in the vertical direction while maintaining a compact footprint, allowing low-noise performance in a smaller device area suitable for image sensor applications.
Data Source
AI summary
The present disclosure provides a transistor structure, including a self-aligned source-drain structure surrounded by an insulating structure and a gate of a second conductive type separated from the source and the drain by the insulating structure. The self-aligned source-drain structure includes a source and a drain of a first conductive type, a channel between the source and the drain, and a polysilicon contact over and aligned with the channel. A method for manufacturing the transistor structure is also provided in the present disclosure.