JFET Shield Layer Layout for Lower Mirror Capacitance
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Solution Overview
Problem
In semiconductor devices with junction field effect transistors (JFETs), the mirror capacitance ratio is high, leading to increased switching loss, which is not effectively reduced by existing manufacturing methods.
Innovation Solution
A method for manufacturing a semiconductor device with a JFET that includes forming a shield layer between the gate and drift layers, maintained at a potential different from the gate layer, using ion-implantation to reduce the mirror capacitance ratio and simplify the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional JFET structure is used, then the device can be manufactured with existing processes, but the mirror capacitance ratio is high leading to increased switching loss
Solution Approach 1:
The gate structure is segmented into two separate gate layers (first gate layer and second gate layer) with different conductivity types, rather than using a single gate structure. This segmentation allows independent optimization of each gate's function, reducing the mirror capacitance ratio and switching loss while maintaining manufacturability through sequential formation processes
Solution Approach 2:
Different regions of the gate structure are assigned different conductivity types (first conductivity type for the first gate layer, second conductivity type for the second gate layer) to optimize local electrical characteristics. This local quality differentiation reduces the mirror capacitance ratio in critical regions while maintaining overall device performance
2Loss of energy
If the mirror capacitance ratio is reduced to decrease switching loss, then energy efficiency improves, but the manufacturing process becomes more complex
Solution Approach 1:
The first gate layer is formed preliminarily before the channel layer, and the second gate layer is formed after the channel layer. This preliminary action sequence allows each gate layer to be formed under optimized conditions without interfering with each other, reducing the mirror capacitance ratio while maintaining a manageable manufacturing process
Solution Approach 2:
The conductivity type parameter is changed between the first gate layer (first conductivity type) and the second gate layer (second conductivity type). This parameter change enables reduction of the mirror capacitance ratio and switching loss while using standard ion implantation or epitaxial growth processes that are already available in manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces the mirror capacitance ratio and switching loss by incorporating a shield layer, allowing for a simpler manufacturing process and improved semiconductor device performance.
Implementation Method 1
using ion-implantation to reduce the mirror capacitance ratio and simplify the manufacturing process
Data Source
AI summary
A method for manufacturing a semiconductor device having a junction field effect transistor, includes: preparing a substrate having a first conductivity type drift layer; forming a first conductivity type channel layer above the drift layer by an epitaxial growth, to thereby produce a semiconductor substrate; forming a second conductivity type gate layer within the channel layer by performing an ion-implantation; forming a second conductivity type body layer at a position separated from the gate layer within the channel layer by performing an ion-implantation; and forming a second conductivity type shield layer at a position that is to be located between the gate layer and the drift layer within the channel layer by performing an ion-implantation. The shield layer is formed to face the gate layer while being separated from the gate layer, and is kept to a potential different from that of the gate layer.