JFET Shielding Layer Pinch-Off Voltage On-Resistance Tradeoff
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Solution Overview
Problem
Existing junction field effect transistors (JFETs) face a tradeoff between reducing pinch-off voltage and maintaining a sufficient distance between the source and gate regions, which complicates fabrication and reduces gate-source breakdown voltage, leading to increased on-resistance.
Innovation Solution
Incorporating a shielding layer of a second doping type in the epitaxial layer between the source and drain regions to enhance the pinch-off effect, reducing pinch-off voltage while maintaining the distance between the source and gate regions, thereby achieving high gate-source breakdown voltage and low on-resistance without performance tradeoffs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of the pinch-off region is reduced to enhance the pinch-off effect, then the pinch-off voltage decreases, but the width of the conductive path is reduced and on-resistance increases
Solution Approach 1:
The patent divides the pinch-off region into two separate regions: a first pinch-off region between the gate region and the source region, and a second pinch-off region between the gate region and the drain region. This segmentation allows independent optimization of each region's characteristics, enabling low pinch-off voltage while maintaining sufficient conductive path width and low on-resistance.
Solution Approach 2:
The patent applies different doping concentrations to different regions: a first doping concentration in the source region and a second doping concentration in the drain region, where the second doping concentration is higher than the first. This local quality differentiation optimizes the electrical characteristics in each region, achieving low pinch-off voltage while maintaining low on-resistance through tailored local properties.
2Reliability
If higher resolution optical lithography is used to reduce pinch-off region width, then pinch-off voltage is reduced, but fabrication process becomes more complicated
Solution Approach 1:
The patent resolves the fabrication complexity issue by changing the doping concentration parameter rather than relying on higher resolution lithography. The different doping concentrations in the source and drain regions can be achieved through standard ion implantation or diffusion processes, avoiding the need for more complex and costly high-resolution lithography equipment while still achieving the desired low pinch-off voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The shielding layer enhances the pinch-off effect, reducing pinch-off voltage while maintaining the distance between the source and gate regions, resulting in improved performance with simpler design by avoiding the tradeoff between pinch-off voltage and on-resistance.
Implementation Method 1
When a bias voltage is applied to the gate contact 108, the P body region 103 will produce a pinch-off effect, so the current flowing through the conductive path can be controlled
Implementation Method 2
an N+ drain region 101, an N− epitaxial layer 102, a P body region 103, an N+ source region 104, and a P+ gate region 105
Data Source
AI summary
A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.