JFET Noise Reduction via STI Channel Separation
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Solution Overview
Problem
Junction field effect transistors (JFETs) face challenges in reducing noise, particularly due to the presence of irregularities, crystal defects, and fixed charges at the interface between the shallow trench isolation (STI) and the channel layer, which generate flicker noise and require additional structures for gate potential application, leading to increased size and complexity.
Innovation Solution
The design includes a p-channel type JFET with a semiconductor substrate, n-well, channel layer, source and drain layers with higher impurity concentrations, and a gate layer, where both ends of the channel layer are separated from the STI, and the gate layer extends between the source and drain, reducing noise by minimizing current flow near the STI and eliminating the need for external gate potential application, thereby allowing miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the channel layer is separated from the STI, then noise is reduced, but the device structure becomes more complex
Solution Approach 1:
The patent extracts the harmful interaction between the channel layer and STI by separating the channel layer from the STI structure. This is achieved by forming the channel layer over the well layer without direct contact with the STI, thereby removing the source of flicker noise generated at the STI-channel interface while maintaining the isolation function of the STI structure.
Solution Approach 2:
The patent implements a nested structure where the channel layer is positioned within the well layer region, and both are contained within the substrate structure. The gate electrode is nested over the channel layer, creating a layered configuration that achieves noise reduction while maintaining compact device geometry.
2Ease of operation
If additional structures are added to apply gate potential, then gate control is improved, but device size increases
Solution Approach 1:
The patent merges the gate electrode structure with the channel layer configuration by positioning the gate electrode directly over the channel layer in a integrated manner. This integration allows the gate potential to be applied effectively through the gate electrode without requiring separate external structures, thereby maintaining compact device size while achieving proper gate control.
Solution Approach 2:
The gate electrode serves multiple functions: it provides gate control over the channel layer, defines the active region boundaries, and integrates with the overall device structure. This multi-functionality eliminates the need for additional dedicated structures for gate potential application, reducing device size while maintaining operational effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces noise in the source and drain current by minimizing flicker noise and allowing for a more compact device structure by applying the gate potential directly through the gate layer, enhancing the transistor's performance and miniaturization capabilities.
Implementation Method 1
a gate layer of a first conductivity type, on the second semiconductor layer, between the source layer and the drain layer, and separated from the source layer and the drain layer
Implementation Method 2
junction field effect transistor
Implementation Method 3
source and drain layers of a second conductivity type, on the second semiconductor layer, and separated from each other in a second direction intersecting the first direction, the source and drain layers having an impurity concentration higher than an impurity concentration of the second semiconductor layer
Data Source
AI summary
A junction field effect transistor includes a first semiconductor layer of first conductivity type, an element isolation insulator disposed on the first semiconductor layer to partition an active area, a second semiconductor layer of second conductivity type, on the first semiconductor layer in the active area, and having an end in a first direction separated from the element isolation insulator, a source layer of second conductivity type, on the second semiconductor layer, the source layer having an impurity concentration higher than that of the second semiconductor layer, a drain layer of second conductivity type, on the second semiconductor layer, and separated from the source layer in a second direction, the drain layer having an impurity concentration higher than that of the second semiconductor layer, and a gate layer of first conductivity type, on the second semiconductor layer, and between and separated from the source and drain layers.