Trench Vertical JFET Threshold Voltage Control via Angled Implantation
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Solution Overview
Problem
Existing vertical junction field-effect transistors (JFETs) face significant variations in threshold voltage due to limitations in epitaxial layer growth and photolithography and etch process variations, leading to fluctuations in doping levels and mesa widths, resulting in large variations in charge resident between gate regions and device threshold voltage.
Innovation Solution
The creation of trench JFETs with angled implantation of vertical channel regions and a lightly doped channel layer between the drift and source layers, which minimizes the impact of epitaxial layer doping and mesa width variations by controlling the charge between gate regions, thereby stabilizing the threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If epitaxial layer growth and photolithography/etch processes are used to create vertical JFETs, then device fabrication is achieved, but threshold voltage variations occur due to doping level and mesa width fluctuations
Solution Approach 1:
The patent changes the doping parameter by introducing a lightly doped channel layer (1e15 to 1e17 atoms/cm³) between the drift and source layers, which is significantly lighter than conventional channel layers. This parameter change makes the threshold voltage insensitive to variations in epitaxial doping and mesa width, as the implanted channel regions dominate the charge control
Solution Approach 2:
The patent introduces an intermediary lightly doped channel layer between the drift and source layers that acts as a mediator to decouple the threshold voltage from variations in the drift layer doping and mesa dimensions. This intermediary layer allows precise control of threshold voltage through angled ion implantation of channel regions independent of the epitaxial process variations
2Ease of operation
If conventional vertical JFET structures are used, then device operation is achieved, but large variations in charge resident between gate regions lead to threshold voltage fluctuations
Solution Approach 1:
The patent segments the channel into distinct regions: a lightly doped channel layer extending between gate regions and heavily doped implanted channel regions formed by angled ion implantation. This segmentation allows the implanted regions to dominate the charge control between gates, making the threshold voltage reliable and consistent despite variations in other structural parameters
Solution Approach 2:
The patent applies local quality by creating heavily doped channel regions through angled ion implantation specifically in the areas between the gate regions, while maintaining a lightly doped channel layer elsewhere. This localized high doping concentration in the channel regions directly controls the threshold voltage, ensuring reliability by dominating the charge resident between gates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces threshold voltage variations, ensuring more consistent device performance by dominating the voltage threshold with implanted channel region charge, thus negating the effects of epitaxial layer and process variations.
Implementation Method 1
a lightly doped channel layer between the drift and source layers... controlling the charge between gate regions
Implementation Method 2
angled implantation using a doping of the first kind, providing improved threshold voltage control
Data Source
AI summary
Trench JFETs may be created by etching trenches into the topside of a substrate of a first doping type to form mesas. The substrate is made up of a backside drain layer, a middle drift layer, and topside source layer. The etching goes through the source layer and partly into the drift layer. Gate regions are formed on the sides and bottoms of the trenches using doping of a second type. Vertical channel regions are formed behind the vertical gate segments via angled implantation using a doping of the first kind, providing improved threshold voltage control. Optionally the substrate may include a lightly doped channel layer between the drift and source layers, such that the mesas include a lightly doped channel region that more strongly contrasts with the implanted vertical channel regions.