JFET Width Defined by Deep Trench Isolation and Bottom Gate
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Solution Overview
Problem
Existing junction field-effect transistors (JFETs) face challenges in achieving high voltage tolerance and efficient process monitoring, particularly in ICs, due to limitations in trench isolation and lateral diffusion measurement, which are typically destructive and time-consuming.
Innovation Solution
The implementation of a JFET design featuring a first deep trench isolation region with a bottom gate sinker that extends laterally and vertically, allowing for non-destructive monitoring of trench depth and lateral diffusion, and enabling high voltage tolerance through a checkerboard layout that reduces lateral diffusion and adjusts pinchoff voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a deep trench isolation region is used to define JFET width, then high voltage tolerance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from planar JFET structures to three-dimensional structures by introducing deep trench isolation regions that extend vertically into the substrate. The trench depth is controlled to be between 0.5-2.0 micrometers, creating a vertical dimension that defines the effective channel width and enables high voltage tolerance while maintaining manufacturability through standard semiconductor processing techniques.
Solution Approach 2:
The invention applies different doping concentrations and trench depths in different regions of the JFET structure. The bottom gate sinker region has higher doping concentration (1E18 to 1E20 atoms/cm³) compared to the channel region, and the trench depth varies to control the effective channel width. This local variation in properties enables simultaneous achievement of high voltage tolerance and controlled electrical characteristics.
2Measurement precision
If destructive methods are used to measure trench depth and lateral diffusion, then measurement accuracy is improved, but production time and cost increase
Solution Approach 1:
The JFET device itself serves as the measurement tool for monitoring trench depth and lateral diffusion. By measuring the electrical characteristics (pinch-off voltage, drain current) of the JFET, information about the trench depth and lateral diffusion extent is obtained without requiring separate destructive cross-sectional analysis. The device structure provides self-diagnostic capability that enables non-destructive process monitoring.
Solution Approach 2:
The invention establishes a feedback mechanism where the electrical characteristics of the JFET are measured and used to infer process parameters such as trench depth and lateral diffusion. This feedback loop allows real-time process monitoring and adjustment without stopping production or using destructive methods, thereby maintaining both measurement accuracy and production efficiency.
3Strength
If lateral diffusion is reduced through checkerboard layout, then voltage tolerance is improved, but device area increases
Solution Approach 1:
The gate structure is segmented into a checkerboard pattern of alternating doped and undoped regions. This segmentation reduces the lateral diffusion of carriers between adjacent regions, thereby improving voltage tolerance. The segmented structure also allows for more efficient packing of multiple JFETs in an integrated circuit, partially offsetting the increased area requirement of individual devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances high voltage tolerance and enables non-destructive process monitoring, providing accurate estimation of trench depth and lateral diffusion without destructive methods, improving the performance and reliability of JFETs in ICs.
Implementation Method 1
A second-type sinker formed in semiconductor surface includes a portion which extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and extends laterally inside the inner first trench wall to provide a bottom gate for the JFET.
Data Source
AI summary
A junction field-effect transistor (JFET) includes a substrate having a first-type semiconductor surface including a topside surface, and a top gate of a second-type formed in the semiconductor surface. A first-type drain and a first-type source are formed on opposing sides of the top gate. A first deep trench isolation region has an inner first trench wall and an outer first trench wall surrounding the top gate, the drain and the source, and extends vertically to a deep trench depth from the topside surface. A second-type sinker formed in semiconductor surface extends laterally outside the outer first trench wall. The sinker extends vertically from the topside surface to a second-type deep portion which is both below the deep trench depth and laterally inside the inner first trench wall to provide a bottom gate.