Just-in-time Cache Associativity for Memory Access

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Solution Overview

Problem

Current cache algorithms face challenges in balancing direct-mapped and set-associative caching, leading to increased read misses and latency due to conflicts between direct-mapped cache's high hit rate for frequently accessed data and set-associative cache's need for tag searches for less frequently accessed data.

Innovation Solution

Implementing a just-in-time cache associativity system that uses direct mapped caching for recently accessed data and switches to set associative caching when conflicts become more common, utilizing a cache manager to determine cache locations and manage remapping information for efficient data placement and retrieval.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If direct mapped caching is used, then hit rate for frequently accessed data is improved, but read misses increase for less frequently accessed data

Engineering Contradiction:
Improvehit rateVSAvoidread misses
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The cache associativity is dynamically adjusted based on access patterns. The system transitions from direct mapped caching (higher hit rate for frequent accesses) to set associative caching (lower read misses for less frequent accesses) using a just-in-time compilation approach that monitors and adapts to data access behavior, resolving the contradiction between maintaining high hit rates and reducing read misses

Inventive Principle:
Principle #15Dynamics

2Productivity

If set associative caching is used, then read misses are reduced, but latency increases due to tag searches

Engineering Contradiction:
Improveread missesVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The system dynamically selects between direct mapped and set associative caching modes based on access frequency analysis. For frequently accessed data, direct mapped caching is used to minimize latency. For less frequently accessed data, set associative caching is employed to reduce read misses, thus balancing latency and read miss reduction

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Different caching strategies are applied to different data based on access patterns. Hot data (frequently accessed) uses direct mapped caching for low latency, while cold data (less frequently accessed) uses set associative caching to reduce misses, allowing each data type to have optimized cache behavior suited to its access characteristics

Inventive Principle:
Principle #3Local quality

3Loss of time

If direct mapped caching is used, then latency is minimized, but cache conflicts increase for multiple addresses

Engineering Contradiction:
ImprovelatencyVSAvoidcache conflicts
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The cache management system dynamically adjusts associativity based on detected conflict patterns. When cache conflicts are detected in direct mapped mode, the system transitions to set associative mode for affected data, reducing conflicts while maintaining low latency for data that remains in direct mapped mode

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The cache associativity parameter is changed based on access patterns and conflict rates. The system monitors cache performance metrics and adjusts the associativity level dynamically, changing from direct mapped (low associativity) to set associative (high associativity) caching based on observed conflict frequencies and access patterns

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3382558B1Apparatus, method and system for just-in-time cache associativity
Publication Date: 2020.01.22 INTEL CORP
  • EP3382558B1 patent drawingFigure 1
  • EP3382558B1 patent drawingFigure 2~4
  • EP3382558B1 patent drawingFigure 5

AI summary

Provided are an apparatus, method, and system for just-in-time cache associativity for a cache memory having cache locations as a cache for a non-volatile memory. Data is received for a target address in the non-volatile memory to add to the cache memory. A determination is made of a direct mapped cache location in the cache memory from the a target address in the non-volatile memory. The data for the target address at an available cache location in the cache memory different from the direct mapped cache location is written in response to the direct mapped cache location storing data for another address in the non-volatile memory. The data for the target address in the direct mapped cache location is written in response to the direct mapped cache location not storing data for another address in the non-volatile memory.